upm  1.6.0
Sensor/Actuator repository for libmraa (v1.9.0)
h3lis331dl.hpp
1 /*
2  * Author: Jon Trulson <jtrulson@ics.com>
3  * Copyright (c) 2015 Intel Corporation.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
20  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 #pragma once
25 
26 #include <string>
27 #include <vector>
28 #include <mraa/common.hpp>
29 #include <mraa/i2c.hpp>
30 
31 #define H3LIS331DL_I2C_BUS 0
32 #define H3LIS331DL_DEFAULT_I2C_ADDR 0x18
33 
34 namespace upm {
35 
59  class H3LIS331DL {
60  public:
61 
65  typedef enum {
66  // Reserved bytes must not be written into as they contain
67  // factory calibration data. Changing those values may lead to
68  // improper functioning of the device.
69 
70  // 0x00-0x0E reserved
71 
72  REG_WHOAMI = 0x0f,
73 
74  // 0x10-0x1f reserved
75 
76  REG_REG1 = 0x20,
77  REG_REG2 = 0x21,
78  REG_REG3 = 0x22,
79  REG_REG4 = 0x23,
80  REG_REG5 = 0x24,
81 
82  REG_HP_FILTER_RESET = 0x25,
83  REG_REFERENCE = 0x26,
84 
85  REG_STATUS = 0x27,
86 
87  REG_OUT_X_L = 0x28,
88  REG_OUT_X_H = 0x29,
89  REG_OUT_Y_L = 0x2a,
90  REG_OUT_Y_H = 0x2b,
91  REG_OUT_Z_L = 0x2c,
92  REG_OUT_Z_H = 0x2d,
93 
94  // 0x2e, 0x2f reserved
95 
96  REG_INT1_CFG = 0x30,
97  REG_INT1_SRC = 0x31,
98  REG_INT1_THS = 0x32,
99  REG_INT1_DUR = 0x33,
100 
101  REG_INT2_CFG = 0x34,
102  REG_INT2_SRC = 0x35,
103  REG_INT2_THS = 0x36,
104  REG_INT2_DUR = 0x37,
105 
106  // 0x38-0x3f reserved
108 
112  typedef enum {
113  REG1_XEN = 0x01, // X-axis enable
114  REG1_YEN = 0x02,
115  REG1_ZEN = 0x04,
116 
117  REG1_DR0 = 0x08, // data rate
118  REG1_DR1 = 0x10,
119  REG1_DR_SHIFT = 3, // DR shift
120 
121  REG1_PM0 = 0x20, // power mode
122  REG1_PM1 = 0x40,
123  REG1_PM2 = 0x80,
124  REG1_PM_SHIFT = 5
125  } REG1_BITS_T;
126 
130  typedef enum {
131  DR_50_37 = 0x0, // 50Hz output with 37Hz LPF cutoff
132  DR_100_74 = 0x1,
133  DR_400_292 = 0x2,
134  DR_1000_780 = 0x3
135  } DR_BITS_T;
136 
140  typedef enum {
141  PM_POWERDWN = 0x0,
142  PM_NORMAL = 0x1,
143  PM_LP05 = 0x2, // .5 updates/sec
144  PM_LP1 = 0x3, // 1 update/sec
145  PM_LP2 = 0x4,
146  PM_LP5 = 0x5,
147  PM_LP10 = 0x6
148  } PM_BITS_T;
149 
153  typedef enum {
154  REG2_HPCF0 = 0x01,
155  REG2_HPCF1 = 0x02,
156  REG2_HPCF_SHIFT = 0,
157 
158  REG2_HPEN1 = 0x04,
159  REG2_HPEN2 = 0x08,
160  REG2_FDS = 0x10,
161 
162  REG2_HPM0 = 0x20,
163  REG2_HPM1 = 0x40,
164  REG2_HPM_SHIFT = 5,
165 
166  REG2_BOOT = 0x80
167  } REG2_BITS_T;
168 
172  typedef enum {
173  HPCF_8 = 0x0,
174  HPCF_16 = 0x1,
175  HPCF_32 = 0x2,
176  HPCF_64 = 0x3,
177  } HPCF_BITS_T;
178 
182  typedef enum {
183  HPM_NORMAL0 = 0x0,
184  HPM_REF = 0x1,
185  HPM_NORMAL1 = 0x2
186  } HPM_BITS_T;
187 
191  typedef enum {
192  REG3_I1_CFG0 = 0x01,
193  REG3_I1_CFG1 = 0x02,
194  REG3_I1_CFG_SHIFT = 0,
195 
196  REG3_LIR1 = 0x04,
197 
198  REG3_I2_CFG0 = 0x08,
199  REG3_I2_CFG1 = 0x10,
200  REG3_I2_CFG_SHIFT = 3,
201 
202  REG3_LIR2 = 0x20,
203  REG3_PP_OD = 0x40,
204  REG3_IHL = 0x80
205  } REG3_BITS_T;
206 
210  typedef enum {
211  I_SRC = 0x0, // INT source
212  I_OR = 0x1, // INT1 OR INT2 source
213  I_DR = 0x2, // Data Ready
214  I_BOOTING = 0x3 // Boot is running
215  } I_CFG_BITS_T;
216 
220  typedef enum {
221  REG4_SIM = 0x01, // SPI 4 or 3 wire
222 
223  // bits 01,02,04 reserved
224 
225  REG4_FS0 = 0x10,
226  REG4_FS1 = 0x20,
227  REG4_FS_SHIFT = 4,
228 
229  REG4_BLE = 0x40, // big/little-endian
230  REG4_BDU = 0x80 // Block data update
231  } REG4_BITS_T;
232 
236  typedef enum {
237  FS_100 = 0x0, // 100g scale
238  FS_200 = 0x1, // 200g scale
239  FS_400 = 0x3 // 400g scale
240  } FS_BITS_T;
241 
245  typedef enum {
246  REG5_TURNON0 = 0x01, // turn-on mode for sleep-to-wake
247  REG5_TURNON1 = 0x02
248 
249  // bits 04-80 reserved
250  } REG5_BITS_T;
251 
255  typedef enum {
256  STATUS_XDA = 0x01, // X data available
257  STATUS_YDA = 0x02,
258  STATUS_ZDA = 0x04,
259  STATUS_ZYXDA = 0x08, // X, Y, and Z data available
260  STATUS_XOR = 0x10, // X overrun
261  STATUS_YOR = 0x20,
262  STATUS_ZOR = 0x40,
263  STATUS_ZYXOR = 0x80 // X, Y, and Z data overrun
264  } STATUS_BITS_T;
265 
269  typedef enum {
270  INT_CFG_XLIE = 0x01, // enable intr on low X event
271  INT_CFG_XHIE = 0x02, // enable intr on high X event
272  INT_CFG_YLIE = 0x04,
273  INT_CFG_YHIE = 0x08,
274  INT_CFG_ZLIE = 0x10,
275  INT_CFG_ZHIE = 0x20,
276  // 0x40 reserved
277  INT_CFG_AOI = 0x80 // AND or OR combination or intrs
278  } INT_CFG_BITS_T;
279 
283  typedef enum {
284  INT_SRC_XL = 0x01, // X low intr event
285  INT_SRC_XH = 0x02, // X high intr event
286  INT_SRC_YL = 0x04,
287  INT_SRC_YH = 0x08,
288  INT_SRC_ZL = 0x10,
289  INT_SRC_ZH = 0x20,
290  INT_SRC_IA = 0x40 // Interrupt generated (active)
291  // 0x80 reserved
292  } INT_SRC_BITS_T;
293 
300  H3LIS331DL(int bus, uint8_t address = H3LIS331DL_DEFAULT_I2C_ADDR);
301 
305  ~H3LIS331DL();
306 
315  bool init(DR_BITS_T odr=DR_50_37, PM_BITS_T pm=PM_NORMAL,
316  FS_BITS_T fs=FS_100);
317 
323  uint8_t getChipID();
324 
331  bool setDataRate(DR_BITS_T odr);
332 
339  bool setPowerMode(PM_BITS_T pm);
340 
350  bool enableAxis(uint8_t axisEnable);
351 
358  bool setFullScale(FS_BITS_T fs);
359 
366  bool setHPCF(HPCF_BITS_T val);
367 
374  bool setHPM(HPM_BITS_T val);
375 
384  bool boot();
385 
392  bool enableHPF1(bool enable);
393 
400  bool enableHPF2(bool enable);
401 
408  bool enableFDS(bool enable);
409 
416  bool setInterruptActiveLow(bool enable);
417 
424  bool setInterruptOpenDrain(bool enable);
425 
432  bool setInterrupt1Latch(bool enable);
433 
440  bool setInterrupt2Latch(bool enable);
441 
449 
457 
466  bool enableBDU(bool enable);
467 
474  bool enableBLE(bool enable);
475 
482  bool enableSleepToWake(bool enable);
483 
489  uint8_t getStatus();
490 
497  bool setInterrupt1Config(uint8_t val);
498 
505  bool setInterrupt2Config(uint8_t val);
506 
513  bool setInterrupt1Source(uint8_t val);
514 
521  bool setInterrupt2Source(uint8_t val);
522 
529  bool setInterrupt1Threshold(uint8_t val);
530 
537  bool setInterrupt2Threshold(uint8_t val);
538 
545  bool setInterrupt1Duration(uint8_t val);
546 
553  bool setInterrupt2Duration(uint8_t val);
554 
558  void update();
559 
569  void setAdjustmentOffsets(int adjX, int adjY, int adjZ);
570 
578  void getAcceleration(float *aX, float *aY, float *aZ);
579 
587  void getRawXYZ(int *x, int *y, int *z);
588 
596  void getXYZ(int *x, int *y, int *z);
597 
603  std::vector<float> getAcceleration();
604 
610  std::vector<int> getRawXYZ();
611 
617  std::vector<int> getXYZ();
618 
625  mraa::I2c& i2cContext() { return m_i2c; };
626 
627 
628  protected:
629  int16_t m_rawX, m_rawY, m_rawZ;
630  int16_t m_adjX, m_adjY, m_adjZ;
631  mraa::I2c m_i2c;
632 
633  private:
634  uint8_t m_addr;
635  };
636 }
637 
638 
uint8_t getStatus()
Definition: h3lis331dl.cxx:432
REG2_BITS_T
Definition: h3lis331dl.hpp:153
I_CFG_BITS_T
Definition: h3lis331dl.hpp:210
DR_BITS_T
Definition: h3lis331dl.hpp:130
uint8_t getChipID()
Definition: h3lis331dl.cxx:78
std::vector< float > getAcceleration()
Definition: h3lis331dl.cxx:603
std::vector< int > getRawXYZ()
Definition: h3lis331dl.cxx:610
H3LIS331DL(int bus, uint8_t address=H3LIS331DL_DEFAULT_I2C_ADDR)
Definition: h3lis331dl.cxx:37
bool setInterrupt1Source(uint8_t val)
Definition: h3lis331dl.cxx:454
bool setInterrupt1Duration(uint8_t val)
Definition: h3lis331dl.cxx:483
bool setFullScale(FS_BITS_T fs)
Definition: h3lis331dl.cxx:134
bool setInterrupt2PadConfig(I_CFG_BITS_T val)
Definition: h3lis331dl.cxx:357
REG5_BITS_T
Definition: h3lis331dl.hpp:245
bool setHPCF(HPCF_BITS_T val)
Definition: h3lis331dl.cxx:151
REG1_BITS_T
Definition: h3lis331dl.hpp:112
bool setInterrupt2Source(uint8_t val)
Definition: h3lis331dl.cxx:512
bool setDataRate(DR_BITS_T odr)
Definition: h3lis331dl.cxx:83
bool enableBDU(bool enable)
Definition: h3lis331dl.cxx:375
std::vector< int > getXYZ()
Definition: h3lis331dl.cxx:617
HPM_BITS_T
Definition: h3lis331dl.hpp:182
bool enableHPF1(bool enable)
Definition: h3lis331dl.cxx:207
H3LIS331DL_REG_T
Definition: h3lis331dl.hpp:65
bool enableHPF2(bool enable)
Definition: h3lis331dl.cxx:226
void update()
Definition: h3lis331dl.cxx:553
bool enableBLE(bool enable)
Definition: h3lis331dl.cxx:394
void setAdjustmentOffsets(int adjX, int adjY, int adjZ)
Definition: h3lis331dl.cxx:573
bool setInterrupt2Threshold(uint8_t val)
Definition: h3lis331dl.cxx:529
bool setInterrupt1Latch(bool enable)
Definition: h3lis331dl.cxx:302
C++ API for the kxtj3 driver.
Definition: a110x.hpp:29
mraa::I2c & i2cContext()
Definition: h3lis331dl.hpp:625
API for the H3LIS331DL-based Grove 3-Axis Digital Accelerometer (400g)
Definition: h3lis331dl.hpp:59
bool boot()
Definition: h3lis331dl.cxx:185
bool enableSleepToWake(bool enable)
Definition: h3lis331dl.cxx:413
bool setInterruptActiveLow(bool enable)
Definition: h3lis331dl.cxx:264
bool setPowerMode(PM_BITS_T pm)
Definition: h3lis331dl.cxx:100
FS_BITS_T
Definition: h3lis331dl.hpp:236
bool setInterrupt1Threshold(uint8_t val)
Definition: h3lis331dl.cxx:471
PM_BITS_T
Definition: h3lis331dl.hpp:140
REG3_BITS_T
Definition: h3lis331dl.hpp:191
STATUS_BITS_T
Definition: h3lis331dl.hpp:255
bool setInterrupt2Duration(uint8_t val)
Definition: h3lis331dl.cxx:541
bool setInterrupt1Config(uint8_t val)
Definition: h3lis331dl.cxx:437
bool setInterrupt2Latch(bool enable)
Definition: h3lis331dl.cxx:321
bool setHPM(HPM_BITS_T val)
Definition: h3lis331dl.cxx:168
bool setInterrupt2Config(uint8_t val)
Definition: h3lis331dl.cxx:495
HPCF_BITS_T
Definition: h3lis331dl.hpp:172
REG4_BITS_T
Definition: h3lis331dl.hpp:220
bool setInterruptOpenDrain(bool enable)
Definition: h3lis331dl.cxx:283
bool init(DR_BITS_T odr=DR_50_37, PM_BITS_T pm=PM_NORMAL, FS_BITS_T fs=FS_100)
Definition: h3lis331dl.cxx:58
bool enableAxis(uint8_t axisEnable)
Definition: h3lis331dl.cxx:117
INT_CFG_BITS_T
Definition: h3lis331dl.hpp:269
~H3LIS331DL()
Definition: h3lis331dl.cxx:54
bool setInterrupt1PadConfig(I_CFG_BITS_T val)
Definition: h3lis331dl.cxx:340
INT_SRC_BITS_T
Definition: h3lis331dl.hpp:283
bool enableFDS(bool enable)
Definition: h3lis331dl.cxx:245