upm  1.7.1
Sensor/Actuator repository for libmraa (v2.0.0)
kx122_registers.h
1 /*
2 The MIT License (MIT)
3 Copyright (c) 2017 Kionix Inc.
4 
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the
7 "Software"), to deal in the Software without restriction, including
8 without limitation the rights to use, copy, modify, merge, publish,
9 distribute, sublicense, and/or sell copies of the Software, and to
10 permit persons to whom the Software is furnished to do so, subject to
11 the following conditions:
12 
13 The above copyright notice and this permission notice shall be included
14 in all copies or substantial portions of the Software.
15 
16 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
19 IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
20 CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24 
25 #ifndef __KX122_REGISTERS_H__
26 #define __KX122_REGISTERS_H__
27 /* registers */
28 // x- hp filter output
29 #define KX122_XHP_L 0x00
30 #define KX122_XHP_H 0x01
31 // y- hp filter output
32 #define KX122_YHP_L 0x02
33 #define KX122_YHP_H 0x03
34 // z- hpfilteroutput
35 #define KX122_ZHP_L 0x04
36 #define KX122_ZHP_H 0x05
37 // output register x
38 #define KX122_XOUT_L 0x06
39 #define KX122_XOUT_H 0x07
40 // output register y
41 #define KX122_YOUT_L 0x08
42 #define KX122_YOUT_H 0x09
43 // output register z
44 #define KX122_ZOUT_L 0x0A
45 #define KX122_ZOUT_H 0x0B
46 // communication selftest
47 #define KX122_COTR 0x0C
48 // WHO_AM_I
49 #define KX122_WHO_AM_I 0x0F
50 // current sixfacet posititions
51 #define KX122_TSCP 0x10
52 // previous six facet positions
53 #define KX122_TSPP 0x11
54 // This register indicates the triggering axis when a tap/double tap interrupt occurs.
55 #define KX122_INS1 0x12
56 // This register tells witch function caused an interrupt.
57 #define KX122_INS2 0x13
58 // This register reports the axis and direction of detected motion.
59 #define KX122_INS3 0x14
60 // This register reports the status of the interrupt.
61 #define KX122_STATUS_REG 0x15
62 #define KX122_INT_REL 0x17
63 // Read/write control register that controls the main feature set.
64 #define KX122_CNTL1 0x18
65 // 2' control register
66 #define KX122_CNTL2 0x19
67 // 3' controlregister
68 #define KX122_CNTL3 0x1A
69 // This register is responsible for configuring ODR (output data rate) and filter settings
70 #define KX122_ODCNTL 0x1B
71 // This register controls the settings for the physical interrupt pin INT1
72 #define KX122_INC1 0x1C
73 // This register controls which axis and direction of detected motion can cause an interrupt.
74 #define KX122_INC2 0x1D
75 // This register controls which axis and direction of tap/double tap can cause an interrup
76 #define KX122_INC3 0x1E
77 // This register controls routing of an interrupt reporting to physical interrupt pin INT1
78 #define KX122_INC4 0x1F
79 // This register controls the settings for the physical interrupt pin INT2.
80 #define KX122_INC5 0x20
81 // This register controls routing of interrupt reporting to physical interrupt pin INT2
82 #define KX122_INC6 0x21
83 #define KX122_TILT_TIMER 0x22
84 #define KX122_WUFC 0x23
85 // This register is responsible for enableing/disabling reporting of Tap/Double Tap.
86 #define KX122_TDTRC 0x24
87 #define KX122_TDTC 0x25
88 #define KX122_TTH 0x26
89 #define KX122_TTL 0x27
90 #define KX122_FTD 0x28
91 #define KX122_STD 0x29
92 #define KX122_TLT 0x2A
93 #define KX122_TWS 0x2B
94 #define KX122_FFTH 0x2C
95 #define KX122_FFC 0x2D
96 // Free Fall Control: This register contains the counter setting of the Free fall detection.
97 #define KX122_FFCNTL 0x2E
98 #define KX122_ATH 0x30
99 #define KX122_TILT_ANGLE_LL 0x32
100 #define KX122_TILT_ANGLE_HL 0x33
101 // This register sets the Hysteresis that is placed in between the Screen Rotation states
102 #define KX122_HYST_SET 0x34
103 // Low Power Control sets the number of samples of accelerometer output to be average
104 #define KX122_LP_CNTL 0x35
105 // Read/write control register that controls the buffer sample threshold
106 #define KX122_BUF_CNTL1 0x3A
107 // Read/write control register that controls sample buffer operation
108 #define KX122_BUF_CNTL2 0x3B
109 // This register reports the status of the sample buffer
110 #define KX122_BUF_STATUS_1 0x3C
111 // This register reports the status of the sample buffer trigger function
112 #define KX122_BUF_STATUS_2 0x3D
113 #define KX122_BUF_CLEAR 0x3E
114 #define KX122_BUF_READ 0x3F
115 // When 0xCA is written to this register, the MEMS self-test function is enabled. Electrostatic-actuation of the accelerometer, results in a DC shift of the X, Y and Z axis outputs. Writing 0x00 to this register will return the accelerometer to normal operation
116 #define KX122_SELF_TEST 0x60
117 // WHO_AM_I
118 #define KX112_WHO_AM_I 0x0F
119 // WHO_AM_I
120 #define KX123_WHO_AM_I 0x0F
121 // WHO_AM_I
122 #define KX124_WHO_AM_I 0x0F
123 /* registers bits */
124 // before set
125 #define KX122_COTR_DCSTR_BEFORE (0x55 << 0)
126 // after set
127 #define KX122_COTR_DCSTR_AFTER (0xAA << 0)
128 // WHO_AM_I -value for KX122
129 #define KX122_WHO_AM_I_WIA_ID (0x1B << 0)
130 // x-left
131 #define KX122_TSCP_LE (0x01 << 5)
132 // x+right
133 #define KX122_TSCP_RI (0x01 << 4)
134 // y-down
135 #define KX122_TSCP_DO (0x01 << 3)
136 // y+up
137 #define KX122_TSCP_UP (0x01 << 2)
138 // z-facedown
139 #define KX122_TSCP_FD (0x01 << 1)
140 // z+faceup
141 #define KX122_TSCP_FU (0x01 << 0)
142 // x-left
143 #define KX122_TSPP_LE (0x01 << 5)
144 // x+right
145 #define KX122_TSPP_RI (0x01 << 4)
146 // y-down
147 #define KX122_TSPP_DO (0x01 << 3)
148 // y+up
149 #define KX122_TSPP_UP (0x01 << 2)
150 // z-facedown
151 #define KX122_TSPP_FD (0x01 << 1)
152 // z+faceup
153 #define KX122_TSPP_FU (0x01 << 0)
154 // x-
155 #define KX122_INS1_TLE (0x01 << 5)
156 // x+
157 #define KX122_INS1_TRI (0x01 << 4)
158 // y-
159 #define KX122_INS1_TDO (0x01 << 3)
160 // y+
161 #define KX122_INS1_TUP (0x01 << 2)
162 // z-
163 #define KX122_INS1_TFD (0x01 << 1)
164 // z+
165 #define KX122_INS1_TFU (0x01 << 0)
166 // Free fall. This bit is cleared when the interrupt latch release register (INL) is read..
167 #define KX122_INS2_FFS (0x01 << 7)
168 // indicates buffer full interrupt. Automatically cleared when buffer is read.
169 #define KX122_INS2_BFI (0x01 << 6)
170 // Watermark interrupt, bit is set to one when FIFO has filled up to the value stored in the sample bits.This bit is automatically cleared when FIFO/FILO is read and the content returns to a value below the value stored in the sample bits.
171 #define KX122_INS2_WMI (0x01 << 5)
172 // indicates that new acceleration data (0x06h to 0x0Bh) is available. This bit is cleared when acceleration data is read or the interrupt release register INT_REL is read.
173 #define KX122_INS2_DRDY (0x01 << 4)
174 // no tap
175 #define KX122_INS2_TDTS_NOTAP (0x00 << 2)
176 // single tap event
177 #define KX122_INS2_TDTS_SINGLE (0x01 << 2)
178 // double tap event
179 #define KX122_INS2_TDTS_DOUBLE (0x02 << 2)
180 // do not exist
181 #define KX122_INS2_TDTS_NA (0x03 << 2)
182 // Status of Wake up. This bit is cleared when the interrupt release register INT_REL is read.
183 #define KX122_INS2_WUFS (0x01 << 1)
184 // Tilt Position status. This bit is cleared when the interrupt release register INT_REL is read.
185 #define KX122_INS2_TPS (0x01 << 0)
186 // x-
187 #define KX122_INS3_XNWU (0x01 << 5)
188 // x+
189 #define KX122_INS3_XPWU (0x01 << 4)
190 // y-
191 #define KX122_INS3_YNWU (0x01 << 3)
192 // y+
193 #define KX122_INS3_YPWU (0x01 << 2)
194 // z-
195 #define KX122_INS3_ZNWU (0x01 << 1)
196 // z+
197 #define KX122_INS3_ZPWU (0x01 << 0)
198 // INT reports the combined (OR) interrupt information of all features.
199 #define KX122_STATUS_REG_INT (0x01 << 4)
200 // controls the operating mode of the KX122.
201 #define KX122_CNTL1_PC1 (0x01 << 7)
202 // determines the performance mode of the KX122. The noise varies with ODR, RES and different LP_CNTL settings possibly reducing the effective resolution.
203 #define KX122_CNTL1_RES (0x01 << 6)
204 // enables the reporting of the availability of new acceleration data as an interrupt
205 #define KX122_CNTL1_DRDYE (0x01 << 5)
206 // 2g range
207 #define KX122_CNTL1_GSEL_2G (0x00 << 3)
208 // 4g range
209 #define KX122_CNTL1_GSEL_4G (0x01 << 3)
210 // 8g range
211 #define KX122_CNTL1_GSEL_8G (0x02 << 3)
212 // not valid settings
213 #define KX122_CNTL1_GSEL_NA (0x03 << 3)
214 // enables the Directional Tap function that will detect single and double tap events.
215 #define KX122_CNTL1_TDTE (0x01 << 2)
216 // enables the Wake Up (motion detect) function
217 #define KX122_CNTL1_WUFE (0x01 << 1)
218 // enables the Tilt Position function that will detect changes in device orientation.
219 #define KX122_CNTL1_TPE (0x01 << 0)
220 // initiates software reset, which performs the RAM reboot routine
221 #define KX122_CNTL2_SRST (0x01 << 7)
222 // command test control
223 #define KX122_CNTL2_COTC (0x01 << 6)
224 // x-
225 #define KX122_CNTL2_LEM (0x01 << 5)
226 // x+
227 #define KX122_CNTL2_RIM (0x01 << 4)
228 // y-
229 #define KX122_CNTL2_DOM (0x01 << 3)
230 // y+
231 #define KX122_CNTL2_UPM (0x01 << 2)
232 // z-
233 #define KX122_CNTL2_FDM (0x01 << 1)
234 // z+
235 #define KX122_CNTL2_FUM (0x01 << 0)
236 // 1.5Hz
237 #define KX122_CNTL3_OTP_1P563 (0x00 << 6)
238 // 6.25Hz
239 #define KX122_CNTL3_OTP_6P25 (0x01 << 6)
240 // 12.5Hz
241 #define KX122_CNTL3_OTP_12P5 (0x02 << 6)
242 // 50Hz
243 #define KX122_CNTL3_OTP_50 (0x03 << 6)
244 // 50Hz
245 #define KX122_CNTL3_OTDT_50 (0x00 << 3)
246 // 100Hz
247 #define KX122_CNTL3_OTDT_100 (0x01 << 3)
248 // 200Hz
249 #define KX122_CNTL3_OTDT_200 (0x02 << 3)
250 // 400Hz
251 #define KX122_CNTL3_OTDT_400 (0x03 << 3)
252 // 12.5Hz
253 #define KX122_CNTL3_OTDT_12P5 (0x04 << 3)
254 // 25Hz
255 #define KX122_CNTL3_OTDT_25 (0x05 << 3)
256 // 800Hz
257 #define KX122_CNTL3_OTDT_800 (0x06 << 3)
258 // 1600Hz
259 #define KX122_CNTL3_OTDT_1600 (0x07 << 3)
260 // 0.78Hz
261 #define KX122_CNTL3_OWUF_0P781 (0x00 << 0)
262 // 1.563Hz
263 #define KX122_CNTL3_OWUF_1P563 (0x01 << 0)
264 // 3.125Hz
265 #define KX122_CNTL3_OWUF_3P125 (0x02 << 0)
266 // 6.25Hz
267 #define KX122_CNTL3_OWUF_6P25 (0x03 << 0)
268 // 12.5Hz
269 #define KX122_CNTL3_OWUF_12P5 (0x04 << 0)
270 // 25Hz
271 #define KX122_CNTL3_OWUF_25 (0x05 << 0)
272 // 50Hz
273 #define KX122_CNTL3_OWUF_50 (0x06 << 0)
274 // 100Hz
275 #define KX122_CNTL3_OWUF_100 (0x07 << 0)
276 // filtering applied
277 #define KX122_ODCNTL_IIR_BYPASS_APPLY (0x00 << 7)
278 // filter bypassed
279 #define KX122_ODCNTL_IIR_BYPASS_BYPASS (0x01 << 7)
280 // filter corner frequency set to ODR/9
281 #define KX122_ODCNTL_LPRO_ODR_9 (0x00 << 6)
282 // filter corner frequency set to ODR/2
283 #define KX122_ODCNTL_LPRO_ODR_2 (0x01 << 6)
284 // 12.5Hz
285 #define KX122_ODCNTL_OSA_12P5 (0x00 << 0)
286 // 25Hz
287 #define KX122_ODCNTL_OSA_25 (0x01 << 0)
288 // 50Hz
289 #define KX122_ODCNTL_OSA_50 (0x02 << 0)
290 // 100Hz
291 #define KX122_ODCNTL_OSA_100 (0x03 << 0)
292 // 200Hz
293 #define KX122_ODCNTL_OSA_200 (0x04 << 0)
294 // 400Hz
295 #define KX122_ODCNTL_OSA_400 (0x05 << 0)
296 // 800Hz
297 #define KX122_ODCNTL_OSA_800 (0x06 << 0)
298 // 1600Hz
299 #define KX122_ODCNTL_OSA_1600 (0x07 << 0)
300 // 0.78Hz
301 #define KX122_ODCNTL_OSA_0P781 (0x08 << 0)
302 // 1.563Hz
303 #define KX122_ODCNTL_OSA_1P563 (0x09 << 0)
304 // 3.125Hz
305 #define KX122_ODCNTL_OSA_3P125 (0x0A << 0)
306 // 6.25Hz
307 #define KX122_ODCNTL_OSA_6P25 (0x0B << 0)
308 // 3200Hz
309 #define KX122_ODCNTL_OSA_3200 (0x0C << 0)
310 // 6400Hz
311 #define KX122_ODCNTL_OSA_6400 (0x0D << 0)
312 // 12800Hz
313 #define KX122_ODCNTL_OSA_12800 (0x0E << 0)
314 // 25600Hz
315 #define KX122_ODCNTL_OSA_25600 (0x0F << 0)
316 // pulse 50us, 10us 1600ODR and over
317 #define KX122_INC1_PWSEL1_50US_10US (0x00 << 6)
318 // 1*OSA period
319 #define KX122_INC1_PWSEL1_1XOSA (0x01 << 6)
320 // 2*OSA period
321 #define KX122_INC1_PWSEL1_2XOSA (0x02 << 6)
322 // 4*OSA period
323 #define KX122_INC1_PWSEL1_4XOSA (0x03 << 6)
324 // enables/disables the physical interrupt
325 #define KX122_INC1_IEN1 (0x01 << 5)
326 // sets the polarity of the physical interrupt pin
327 #define KX122_INC1_IEA1 (0x01 << 4)
328 // sets the response of the physical interrupt pin
329 #define KX122_INC1_IEL1 (0x01 << 3)
330 // sets the polarity of Self Test
331 #define KX122_INC1_STPOL (0x01 << 1)
332 // sets the 3-wire SPI interface
333 #define KX122_INC1_SPI3E (0x01 << 0)
334 // OR combination between selected directions
335 #define KX122_INC2_AOI_OR (0x00 << 6)
336 // AND combination between selected axes
337 #define KX122_INC2_AOI_AND (0x01 << 6)
338 // x negative (x-): 0 = disabled, 1 = enabled
339 #define KX122_INC2_XNWUE (0x01 << 5)
340 // x positive (x+): 0 = disabled, 1 = enabled
341 #define KX122_INC2_XPWUE (0x01 << 4)
342 // y negative (y-): 0 = disabled, 1 = enabled
343 #define KX122_INC2_YNWUE (0x01 << 3)
344 // y positive (y+): 0 = disabled, 1 = enabled
345 #define KX122_INC2_YPWUE (0x01 << 2)
346 // z negative (z-): 0 = disabled, 1 = enabled
347 #define KX122_INC2_ZNWUE (0x01 << 1)
348 // z positive (z+): 0 = disabled, 1 = enabled
349 #define KX122_INC2_ZPWUE (0x01 << 0)
350 // x negative (x-): 0 = disabled, 1 = enabled
351 #define KX122_INC3_TLEM (0x01 << 5)
352 // x positive (x+): 0 = disabled, 1 = enabled
353 #define KX122_INC3_TRIM (0x01 << 4)
354 // y negative (y-): 0 = disabled, 1 = enabled
355 #define KX122_INC3_TDOM (0x01 << 3)
356 // y positive (y+): 0 = disabled, 1 = enabled
357 #define KX122_INC3_TUPM (0x01 << 2)
358 // z negative (z-): 0 = disabled, 1 = enabled
359 #define KX122_INC3_TFDM (0x01 << 1)
360 // z positive (z+): 0 = disabled, 1 = enabled
361 #define KX122_INC3_TFUM (0x01 << 0)
362 // Free fall interrupt reported on physical interrupt INT1
363 #define KX122_INC4_FFI1 (0x01 << 7)
364 // Buffer full interrupt reported on physical interrupt pin INT1
365 #define KX122_INC4_BFI1 (0x01 << 6)
366 // Watermark interrupt reported on physical interrupt pin INT1
367 #define KX122_INC4_WMI1 (0x01 << 5)
368 // Data ready interrupt reported on physical interrupt pin INT1
369 #define KX122_INC4_DRDYI1 (0x01 << 4)
370 // Tap/Double Tap interrupt reported on physical interrupt pin INT1
371 #define KX122_INC4_TDTI1 (0x01 << 2)
372 // Wake-Up (motion detect) interrupt reported on physical interrupt pin INT1
373 #define KX122_INC4_WUFI1 (0x01 << 1)
374 // Tilt position interrupt reported on physical interrupt pin INT1
375 #define KX122_INC4_TPI1 (0x01 << 0)
376 // pulse 50us, 10us 1600ODR and over
377 #define KX122_INC5_PWSEL2_50US_10US (0x00 << 6)
378 // 1*OSA period
379 #define KX122_INC5_PWSEL2_1XOSA (0x01 << 6)
380 // 2*OSA period
381 #define KX122_INC5_PWSEL2_2XOSA (0x02 << 6)
382 // 4*OSA period
383 #define KX122_INC5_PWSEL2_4XOSA (0x03 << 6)
384 // enables/disables the physical interrupt
385 #define KX122_INC5_IEN2 (0x01 << 5)
386 // sets the polarity of the physical interrupt pin
387 #define KX122_INC5_IEA2 (0x01 << 4)
388 // sets the response of the physical interrupt pin
389 #define KX122_INC5_IEL2 (0x01 << 3)
390 // Interrupt source automatic clear at interup 2 trailing edge
391 #define KX122_INC5_ACLR2 (0x01 << 1)
392 // Interrupt source automatic clear at interup 1 trailing edge
393 #define KX122_INC5_ACLR1 (0x01 << 0)
394 // FFI2 Free fall interrupt reported on physical interrupt INT2
395 #define KX122_INC6_FFI2 (0x01 << 7)
396 // BFI2 Buffer full interrupt reported on physical interrupt pin INT2
397 #define KX122_INC6_BFI2 (0x01 << 6)
398 // WMI2 - Watermark interrupt reported on physical interrupt pin INT2
399 #define KX122_INC6_WMI2 (0x01 << 5)
400 // DRDYI2 Data ready interrupt reported on physical interrupt pin INT2
401 #define KX122_INC6_DRDYI2 (0x01 << 4)
402 // TDTI2 - Tap/Double Tap interrupt reported on physical interrupt pin INT2
403 #define KX122_INC6_TDTI2 (0x01 << 2)
404 // WUFI2 Wake-Up (motion detect) interrupt reported on physical interrupt pin INT2
405 #define KX122_INC6_WUFI2 (0x01 << 1)
406 // TPI2 Tilt position interrupt reported on physical interrupt pin INT2
407 #define KX122_INC6_TPI2 (0x01 << 0)
408 // enables/disables the double tap interrupt
409 #define KX122_TDTRC_DTRE (0x01 << 1)
410 // enables/disables single tap interrupt
411 #define KX122_TDTRC_STRE (0x01 << 0)
412 // Free fall engine enable
413 #define KX122_FFCNTL_FFIE (0x01 << 7)
414 // Free fall interrupt latch/un-latch control
415 #define KX122_FFCNTL_ULMODE (0x01 << 6)
416 // Debounce methodology control
417 #define KX122_FFCNTL_DCRM (0x01 << 3)
418 // 12.5Hz
419 #define KX122_FFCNTL_OFFI_12P5 (0x00 << 0)
420 // 25Hz
421 #define KX122_FFCNTL_OFFI_25 (0x01 << 0)
422 // 50Hz
423 #define KX122_FFCNTL_OFFI_50 (0x02 << 0)
424 // 100Hz
425 #define KX122_FFCNTL_OFFI_100 (0x03 << 0)
426 // 200Hz
427 #define KX122_FFCNTL_OFFI_200 (0x04 << 0)
428 // 400Hz
429 #define KX122_FFCNTL_OFFI_400 (0x05 << 0)
430 // 800Hz
431 #define KX122_FFCNTL_OFFI_800 (0x06 << 0)
432 // 1600Hz
433 #define KX122_FFCNTL_OFFI_1600 (0x07 << 0)
434 // No Averaging
435 #define KX122_LP_CNTL_AVC_NO_AVG (0x00 << 4)
436 // 2 Samples Averaged
437 #define KX122_LP_CNTL_AVC_2_SAMPLE_AVG (0x01 << 4)
438 // 4 Samples Averaged
439 #define KX122_LP_CNTL_AVC_4_SAMPLE_AVG (0x02 << 4)
440 // 8 Samples Averaged
441 #define KX122_LP_CNTL_AVC_8_SAMPLE_AVG (0x03 << 4)
442 // 16 Samples Averaged (default)
443 #define KX122_LP_CNTL_AVC_16_SAMPLE_AVG (0x04 << 4)
444 // 32 Samples Averaged
445 #define KX122_LP_CNTL_AVC_32_SAMPLE_AVG (0x05 << 4)
446 // 64 Samples Averaged
447 #define KX122_LP_CNTL_AVC_64_SAMPLE_AVG (0x06 << 4)
448 // 128 Samples Averaged
449 #define KX122_LP_CNTL_AVC_128_SAMPLE_AVG (0x07 << 4)
450 #define KX122_BUF_CNTL1_SMP_TH0_7 (0xFF << 0)
451 // controls activation of the sample buffer
452 #define KX122_BUF_CNTL2_BUFE (0x01 << 7)
453 // determines the resolution of the acceleration data samples collected by the sample
454 #define KX122_BUF_CNTL2_BRES (0x01 << 6)
455 // buffer full interrupt enable bit
456 #define KX122_BUF_CNTL2_BFIE (0x01 << 5)
457 // watermark level bits 8 and 9
458 #define KX122_BUF_CNTL2_SMP_TH8_9 (0x0C << 2)
459 // The buffer collects 681 sets of 8-bit low resolution values or 339 sets of 16-bit high resolution values and then stops collecting data, collecting new data only when the buffer is not full
460 #define KX122_BUF_CNTL2_BUF_M_FIFO (0x00 << 0)
461 // The buffer holds the last 681 sets of 8-bit low resolution values or 339 sets of 16-bit high resolution values. Once the buffer is full, the oldest data is discarded to make room for newer data.
462 #define KX122_BUF_CNTL2_BUF_M_STREAM (0x01 << 0)
463 // When a trigger event occurs, the buffer holds the last data set of SMP[9:0] samples before the trigger event and then continues to collect data until full. New data is collected only when the buffer is not full.
464 #define KX122_BUF_CNTL2_BUF_M_TRIGGER (0x02 << 0)
465 // The buffer holds the last 681 sets of 8-bit low resolution values or 339 sets of 16-bit high resolution values. Once the buffer is full, the oldest data is discarded to make room for newer data. Reading from the buffer in this mode will return the most recent data first.
466 #define KX122_BUF_CNTL2_BUF_M_FILO (0x03 << 0)
467 #define KX122_BUF_STATUS_1_SMP_LEV0_7 (0xFF << 0)
468 // reports the status of the buffers trigger function if this mode has been selected
469 #define KX122_BUF_STATUS_2_BUF_TRIG (0x01 << 7)
470 // level High mask
471 #define KX122_BUF_STATUS_2_SMP_LEV8_10 (0x07 << 0)
472 // MEMS Test OFF
473 #define KX122_SELF_TEST_MEMS_TEST_OFF (0x00 << 0)
474 // MEMS Test ON
475 #define KX122_SELF_TEST_MEMS_TEST_ON (0xCA << 0)
476 // WHO_AM_I -value for KX112
477 #define KX112_WHO_AM_I_WIA_ID (0x22 << 0)
478 // WHO_AM_I -value for KX123
479 #define KX123_WHO_AM_I_WIA_ID (0x20 << 0)
480 // WHO_AM_I -value for KX124
481 #define KX124_WHO_AM_I_WIA_ID (0x28 << 0)
482  /*registers bit masks */
483 
484 #define KX122_COTR_DCSTR_MASK 0xFF
485 
486 #define KX122_WHO_AM_I_WIA_MASK 0xFF
487 // status of tap/double tap, bit is released when interrupt release register INT_REL is read.
488 #define KX122_INS2_TDTS_MASK 0x0C
489 // selects the acceleration range of the accelerometer outputs
490 #define KX122_CNTL1_GSEL_MASK 0x18
491 // sets the output data rate for the Tilt Position function
492 #define KX122_CNTL3_OTP_MASK 0xC0
493 // sets the output data rate for the Directional TapTM function
494 #define KX122_CNTL3_OTDT_MASK 0x38
495 // sets the output data rate for the general motion detection function and the high-pass filtered outputs
496 #define KX122_CNTL3_OWUF_MASK 0x07
497 // filter bypass mode
498 #define KX122_ODCNTL_IIR_BYPASS_MASK 0x80
499 // low-pass filter roll off control
500 #define KX122_ODCNTL_LPRO_MASK 0x40
501 // acceleration output data rate.
502 #define KX122_ODCNTL_OSA_MASK 0x0F
503 // Pulse interrupt 1 width configuration
504 #define KX122_INC1_PWSEL1_MASK 0xC0
505 // AND OR configuration for motion detection
506 #define KX122_INC2_AOI_MASK 0x40
507 #define KX122_INC2_WUE_MASK 0x3F
508 #define KX122_INC3_TM_MASK 0x3F
509 // Pulse interrupt 2 width configuration
510 #define KX122_INC5_PWSEL2_MASK 0xC0
511 // Output Data Rate at which the Free fall engine performs its function.
512 #define KX122_FFCNTL_OFFI_MASK 0x07
513 #define KX122_HYST_SET_HYST_MASK 0x3F
514 // Averaging Filter Control
515 #define KX122_LP_CNTL_AVC_MASK 0x70
516 
517 #define KX122_BUF_CNTL1_SMP_TH0_MASK 0xFF
518 #define KX122_BUF_CNTL1_SMP_TH0_7_MASK 0xFF
519 
520 #define KX122_BUF_CNTL2_SMP_TH8_MASK 0x0C
521 #define KX122_BUF_CNTL2_SMP_TH8_9_MASK 0x0C
522 // selects the operating mode of the sample buffer
523 #define KX122_BUF_CNTL2_BUF_M_MASK 0x03
524 
525 #define KX122_BUF_STATUS_1_SMP_LEV0_MASK 0xFF
526 #define KX122_BUF_STATUS_1_SMP_LEV0_7_MASK 0xFF
527 
528 #define KX122_BUF_STATUS_2_SMP_LEV8_MASK 0x07
529 #define KX122_BUF_STATUS_2_SMP_LEV8_10_MASK 0x07
530 
531 #define KX122_SELF_TEST_MEMS_TEST_MASK 0xFF
532 
533 #define KX112_WHO_AM_I_WIA_MASK 0xFF
534 
535 #define KX123_WHO_AM_I_WIA_MASK 0xFF
536 
537 #define KX124_WHO_AM_I_WIA_MASK 0xFF
538 #endif
539