upm  1.7.1
Sensor/Actuator repository for libmraa (v2.0.0)
lis3dh_defs.h
1 /*
2  * Author: Alex Tereschenko <alext.mkrs@gmail.com>
3  * Copyright (c) 2018 Alex Tereschenko.
4  *
5  * Based on LIS2DS12 module by
6  * Author: Jon Trulson <jtrulson@ics.com>
7  * Copyright (c) 2017 Intel Corporation.
8  *
9  * The MIT License
10  *
11  * Permission is hereby granted, free of charge, to any person obtaining
12  * a copy of this software and associated documentation files (the
13  * "Software"), to deal in the Software without restriction, including
14  * without limitation the rights to use, copy, modify, merge, publish,
15  * distribute, sublicense, and/or sell copies of the Software, and to
16  * permit persons to whom the Software is furnished to do so, subject to
17  * the following conditions:
18  *
19  * The above copyright notice and this permission notice shall be
20  * included in all copies or substantial portions of the Software.
21  *
22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
26  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
27  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
28  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29  */
30 #pragma once
31 
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 #define LIS3DH_DEFAULT_I2C_BUS 0
37 #define LIS3DH_DEFAULT_SPI_BUS 0
38 #define LIS3DH_DEFAULT_I2C_ADDR 0x18
39 
40 #define LIS3DH_CHIPID 0x33
41 
42 // NOTE: Reserved registers must not be written into or permanent
43 // damage can result. Reading from them may return indeterminate
44 // values. Registers containing reserved bitfields must be
45 // written as 0, except for CTRL_REG0 - see datasheet for that one.
46 
50 typedef enum {
51  // 0x00-0x06 reserved
52 
53  LIS3DH_REG_STATUS_REG_AUX = 0x07,
54 
55  LIS3DH_REG_OUT_ADC1_L = 0x08,
56  LIS3DH_REG_OUT_ADC1_H = 0x09,
57  LIS3DH_REG_OUT_ADC2_L = 0x0A,
58  LIS3DH_REG_OUT_ADC2_H = 0x0B,
59  LIS3DH_REG_OUT_ADC3_L = 0x0C,
60  LIS3DH_REG_OUT_ADC3_H = 0x0D,
61 
62  // 0x0E reserved
63 
64  LIS3DH_REG_WHO_AM_I = 0x0F,
65 
66  // 0x10-0x1D reserved
67 
68  LIS3DH_REG_CTRL_REG0 = 0x1E,
69  LIS3DH_REG_TEMP_CFG_REG = 0x1F,
70  LIS3DH_REG_CTRL_REG1 = 0x20,
71  LIS3DH_REG_CTRL_REG2 = 0x21,
72  LIS3DH_REG_CTRL_REG3 = 0x22,
73  LIS3DH_REG_CTRL_REG4 = 0x23,
74  LIS3DH_REG_CTRL_REG5 = 0x24,
75  LIS3DH_REG_CTRL_REG6 = 0x25,
76 
77  LIS3DH_REG_REFERENCE = 0x26,
78 
79  LIS3DH_REG_STATUS_REG = 0x27,
80 
81  LIS3DH_REG_OUT_X_L = 0x28,
82  LIS3DH_REG_OUT_X_H = 0x29,
83  LIS3DH_REG_OUT_Y_L = 0x2A,
84  LIS3DH_REG_OUT_Y_H = 0x2B,
85  LIS3DH_REG_OUT_Z_L = 0x2C,
86  LIS3DH_REG_OUT_Z_H = 0x2D,
87 
88  LIS3DH_REG_FIFO_CTRL_REG = 0x2E,
89  LIS3DH_REG_FIFO_SRC_REG = 0x2F,
90 
91  LIS3DH_REG_INT1_CFG = 0x30,
92  LIS3DH_REG_INT1_SRC = 0x31,
93  LIS3DH_REG_INT1_THS = 0x32,
94  LIS3DH_REG_INT1_DURATION = 0x33,
95 
96  LIS3DH_REG_INT2_CFG = 0x34,
97  LIS3DH_REG_INT2_SRC = 0x35,
98  LIS3DH_REG_INT2_THS = 0x36,
99  LIS3DH_REG_INT2_DURATION = 0x37,
100 
101  LIS3DH_REG_CLICK_CFG = 0x38,
102  LIS3DH_REG_CLICK_SRC = 0x39,
103  LIS3DH_REG_CLICK_THS = 0x3A,
104 
105  LIS3DH_REG_TIME_LIMIT = 0x3B,
106  LIS3DH_REG_TIME_LATENCY = 0x3C,
107  LIS3DH_REG_TIME_WINDOW = 0x3D,
108 
109  LIS3DH_REG_ACT_THS = 0x3E,
110  LIS3DH_REG_ACT_DUR = 0x3F,
111 } LIS3DH_REGS_T;
112 
116 typedef enum {
117  LIS3DH_STATUS_REG_AUX_1DA = 0x01,
118  LIS3DH_STATUS_REG_AUX_2DA = 0x02,
119  LIS3DH_STATUS_REG_AUX_3DA = 0x04,
120  LIS3DH_STATUS_REG_AUX_321DA = 0x08,
121 
122  LIS3DH_STATUS_REG_AUX_1OR = 0x10,
123  LIS3DH_STATUS_REG_AUX_2OR = 0x20,
124  LIS3DH_STATUS_REG_AUX_3OR = 0x40,
125  LIS3DH_STATUS_REG_AUX_321OR = 0x80,
126 } LIS3DH_STATUS_REG_AUX_BITS_T;
127 
131 typedef enum {
132  // 0x01-0x40 reserved
133 
134  LIS3DH_CTRL_REG0_SDO_PU_DISC = 0x80,
135 } LIS3DH_CTRL_REG0_BITS_T;
136 
140 typedef enum {
141  // 0x01-0x20 reserved
142 
143  LIS3DH_TEMP_CFG_REG_TEMP_EN = 0x40,
144  LIS3DH_TEMP_CFG_REG_ADC_EN = 0x80,
145 } LIS3DH_TEMP_CFG_REG_BITS_T;
146 
150 typedef enum {
151  LIS3DH_CTRL_REG1_XEN = 0x01,
152  LIS3DH_CTRL_REG1_YEN = 0x02,
153  LIS3DH_CTRL_REG1_ZEN = 0x04,
154  LIS3DH_CTRL_REG1_LPEN = 0x08,
155 
156  LIS3DH_CTRL_REG1_ODR0 = 0x10,
157  LIS3DH_CTRL_REG1_ODR1 = 0x20,
158  LIS3DH_CTRL_REG1_ODR2 = 0x40,
159  LIS3DH_CTRL_REG1_ODR3 = 0x80,
160  _LIS3DH_CTRL_REG1_ODR_MASK = 0xF,
161  _LIS3DH_CTRL_REG1_ODR_SHIFT = 4,
162 } LIS3DH_CTRL_REG1_BITS_T;
163 
167 typedef enum {
168  LIS3DH_ODR_POWER_DOWN = 0x0, // 0b0000
169 
170  // These are allowed in all modes (high resolution/normal/low power)
171  LIS3DH_ODR_1HZ = 0x1, // 0b0001
172  LIS3DH_ODR_10HZ = 0x2, // 0b0010
173  LIS3DH_ODR_25HZ = 0x3, // 0b0011
174  LIS3DH_ODR_50HZ = 0x4, // 0b0100
175  LIS3DH_ODR_100HZ = 0x5, // 0b0101
176  LIS3DH_ODR_200HZ = 0x6, // 0b0110
177  LIS3DH_ODR_400HZ = 0x7, // 0b0111
178 
179  // The following two items have a dual meaning depending
180  // on whether the LPEN bit is set, but they use the same
181  // overlapping ODR values for the ODR bitfield. Since the
182  // bitfield is only 4 bits wide, we add a "virtual" 5th bit to
183  // indicate the LP versions. This is then screened out in the
184  // code and will set the LPEN bit according to what is selected
185  // here.
186 
187  // CTRL_REG1_LPEN == 0 (high resolution/normal mode)
188  LIS3DH_ODR_1344HZ = 0x9, // 0b1001
189 
190  // CTRL_REG1_LPEN == 1 (low power mode). Add 'virtual' bit 5
191  // value (0x10) for these LP modes, which we will detect and
192  // screen out in the driver. This simplifies the ODR API.
193  LIS3DH_ODR_5376HZ = (0x10 + 0x9), // 0b1001
194 
195  // Low power-only mode, requires LPEN == 1, so add the virtual bit
196  LIS3DH_ODR_LP_1600HZ = (0x10 + 0x8), // 0b1000
197 } LIS3DH_ODR_T;
198 
202 typedef enum {
203  LIS3DH_CTRL_REG2_HP_IA1 = 0x01,
204  LIS3DH_CTRL_REG2_HP_IA2 = 0x02,
205  LIS3DH_CTRL_REG2_HPCLICK = 0x04,
206  LIS3DH_CTRL_REG2_FDS = 0x08,
207 
208  LIS3DH_CTRL_REG2_HPCF0 = 0x10,
209  LIS3DH_CTRL_REG2_HPCF1 = 0x20,
210  _LIS3DH_CTRL_REG2_HPCF_MASK = 0x3, // 0b11
211  _LIS3DH_CTRL_REG2_HPCF_SHIFT = 4,
212 
213  LIS3DH_CTRL_REG2_HPM0 = 0x40,
214  LIS3DH_CTRL_REG2_HPM1 = 0x80,
215  _LIS3DH_CTRL_REG2_HPM_MASK = 0x3, // 0b11
216  _LIS3DH_CTRL_REG2_HPM_SHIFT = 6,
217 } LIS3DH_CTRL_REG2_BITS_T;
218 
222 typedef enum {
223  LIS3DH_HPM_NORMAL_RST_REF_READ = 0x0, // 0b00, Normal mode (reset by reading REFERENCE)
224  LIS3DH_HPM_REF_SIGNAL = 0x1, // 0b01, Reference signal for filtering
225  LIS3DH_HPM_NORMAL = 0x2, // 0b10, Normal mode
226  LIS3DH_HPM_AUTORST = 0x3, // 0b11, Autoreset on interrupt event
227 } LIS3DH_HPM_T;
228 
232 typedef enum {
233  // 0x01 reserved
234 
235  LIS3DH_CTRL_REG3_I1_OVERRUN = 0x02,
236  LIS3DH_CTRL_REG3_I1_WTM = 0x04,
237  LIS3DH_CTRL_REG3_I1_321DA = 0x08,
238  LIS3DH_CTRL_REG3_I1_ZYXDA = 0x10,
239  LIS3DH_CTRL_REG3_I1_IA2 = 0x20,
240  LIS3DH_CTRL_REG3_I1_IA1 = 0x40,
241  LIS3DH_CTRL_REG3_I1_CLICK = 0x80,
242 } LIS3DH_CTRL_REG3_BITS_T;
243 
247 typedef enum {
248  LIS3DH_CTRL_REG4_SIM = 0x01,
249 
250  LIS3DH_CTRL_REG4_ST0 = 0x02,
251  LIS3DH_CTRL_REG4_ST1 = 0x04,
252  _LIS3DH_CTRL_REG4_ST_MASK = 0x3, // 0b11
253  _LIS3DH_CTRL_REG4_ST_SHIFT = 1,
254 
255  LIS3DH_CTRL_REG4_HR = 0x08,
256 
257  LIS3DH_CTRL_REG4_FS0 = 0x10,
258  LIS3DH_CTRL_REG4_FS1 = 0x20,
259  _LIS3DH_CTRL_REG4_FS_MASK = 0x3, // 0b11
260  _LIS3DH_CTRL_REG4_FS_SHIFT = 4,
261 
262  LIS3DH_CTRL_REG4_BLE = 0x40,
263  LIS3DH_CTRL_REG4_BDU = 0x80,
264 } LIS3DH_CTRL_REG4_BITS_T;
265 
269 typedef enum {
270  LIS3DH_ST_NORMAL = 0x0, // 0b00
271  LIS3DH_ST_ST0 = 0x1, // 0b01
272  LIS3DH_ST_ST1 = 0x2, // 0b10
273 } LIS3DH_ST_T;
274 
278 typedef enum {
279  LIS3DH_FS_2G = 0x0, // 0b00
280  LIS3DH_FS_4G = 0x1, // 0b01
281  LIS3DH_FS_8G = 0x2, // 0b10
282  LIS3DH_FS_16G = 0x3, // 0b11
283 } LIS3DH_FS_T;
284 
288 typedef enum {
289  LIS3DH_CTRL_REG5_D4D_INT2 = 0x01,
290  LIS3DH_CTRL_REG5_LIR_INT2 = 0x02,
291  LIS3DH_CTRL_REG5_D4D_INT1 = 0x04,
292  LIS3DH_CTRL_REG5_LIR_INT1 = 0x08,
293 
294  // 0x10-0x20 reserved
295 
296  LIS3DH_CTRL_REG5_FIFO_EN = 0x40,
297  LIS3DH_CTRL_REG5_BOOT = 0x80,
298 } LIS3DH_CTRL_REG5_BITS_T;
299 
303 typedef enum {
304  // 0x01 reserved
305 
306  LIS3DH_CTRL_REG6_INT_POLARITY = 0x02,
307 
308  // 0x04 reserved
309 
310  LIS3DH_CTRL_REG6_I2_ACT = 0x08,
311  LIS3DH_CTRL_REG6_I2_BOOT = 0x10,
312  LIS3DH_CTRL_REG6_I2_IA2 = 0x20,
313  LIS3DH_CTRL_REG6_I2_IA1 = 0x40,
314  LIS3DH_CTRL_REG6_I2_CLICK = 0x80,
315 } LIS3DH_CTRL_REG6_BITS_T;
316 
320 typedef enum {
321  LIS3DH_STATUS_REG_XDA = 0x01,
322  LIS3DH_STATUS_REG_YDA = 0x02,
323  LIS3DH_STATUS_REG_ZDA = 0x04,
324  LIS3DH_STATUS_REG_ZYXDA = 0x08,
325 
326  LIS3DH_STATUS_REG_XOR = 0x10,
327  LIS3DH_STATUS_REG_YOR = 0x20,
328  LIS3DH_STATUS_REG_ZOR = 0x40,
329  LIS3DH_STATUS_REG_ZYXOR = 0x80,
330 } LIS3DH_STATUS_REG_BITS_T;
331 
335 typedef enum {
336  LIS3DH_FIFO_CTRL_REG_FTH0 = 0x01,
337  LIS3DH_FIFO_CTRL_REG_FTH1 = 0x02,
338  LIS3DH_FIFO_CTRL_REG_FTH2 = 0x04,
339  LIS3DH_FIFO_CTRL_REG_FTH3 = 0x08,
340  LIS3DH_FIFO_CTRL_REG_FTH4 = 0x10,
341  _LIS3DH_FIFO_CTRL_REG_FTH_MASK = 0x1F, // 0b11111
342  _LIS3DH_FIFO_CTRL_REG_FTH_SHIFT = 0,
343 
344  LIS3DH_FIFO_CTRL_REG_TR = 0x20,
345 
346  LIS3DH_FIFO_CTRL_REG_FM0 = 0x40,
347  LIS3DH_FIFO_CTRL_REG_FM1 = 0x80,
348  _LIS3DH_FIFO_CTRL_REG_FM_MASK = 0x3, // 0b11
349  _LIS3DH_FIFO_CTRL_REG_FM_SHIFT = 6,
350 } LIS3DH_FIFO_CTRL_REG_BITS_T;
351 
355 typedef enum {
356  LIS3DH_FM_BYPASS = 0x0, // 0b00
357  LIS3DH_FM_FIFO = 0x1, // 0b01
358  LIS3DH_FM_STREAM = 0x2, // 0b10
359  LIS3DH_FM_STREAM_TO_FIFO = 0x3, // 0b11
360 } LIS3DH_FM_T;
361 
365 typedef enum {
366  LIS3DH_FIFO_SRC_REG_FSS0 = 0x01,
367  LIS3DH_FIFO_SRC_REG_FSS1 = 0x02,
368  LIS3DH_FIFO_SRC_REG_FSS2 = 0x04,
369  LIS3DH_FIFO_SRC_REG_FSS3 = 0x08,
370  LIS3DH_FIFO_SRC_REG_FSS4 = 0x10,
371  _LIS3DH_FIFO_SRC_REG_FSS_MASK = 0x1F, // 0b11111
372  _LIS3DH_FIFO_SRC_REG_FSS_SHIFT = 0,
373 
374  LIS3DH_FIFO_SRC_REG_EMPTY = 0x20,
375  LIS3DH_FIFO_SRC_REG_OVRN_FIFO = 0x40,
376  LIS3DH_FIFO_SRC_REG_WTM = 0x80,
377 } LIS3DH_FIFO_SRC_REG_BITS_T;
378 
382 typedef enum {
383  LIS3DH_INT1_CFG_XLIE = 0x01,
384  LIS3DH_INT1_CFG_XHIE = 0x02,
385 
386  LIS3DH_INT1_CFG_YLIE = 0x04,
387  LIS3DH_INT1_CFG_YHIE = 0x08,
388 
389  LIS3DH_INT1_CFG_ZLIE = 0x10,
390  LIS3DH_INT1_CFG_ZHIE = 0x20,
391 
392  LIS3DH_INT1_CFG_6D = 0x40,
393  LIS3DH_INT1_CFG_AOI = 0x80,
394 } LIS3DH_INT1_CFG_BITS_T;
395 
399 typedef enum {
400  LIS3DH_INT1_SRC_XL = 0x01,
401  LIS3DH_INT1_SRC_XH = 0x02,
402 
403  LIS3DH_INT1_SRC_YL = 0x04,
404  LIS3DH_INT1_SRC_YH = 0x08,
405 
406  LIS3DH_INT1_SRC_ZL = 0x10,
407  LIS3DH_INT1_SRC_ZH = 0x20,
408 
409  LIS3DH_INT1_SRC_IA = 0x40,
410 
411  // 0x80 reserved
412 } LIS3DH_INT1_SRC_BITS_T;
413 
417 typedef enum {
418  LIS3DH_INT2_CFG_XLIE = 0x01,
419  LIS3DH_INT2_CFG_XHIE = 0x02,
420 
421  LIS3DH_INT2_CFG_YLIE = 0x04,
422  LIS3DH_INT2_CFG_YHIE = 0x08,
423 
424  LIS3DH_INT2_CFG_ZLIE = 0x10,
425  LIS3DH_INT2_CFG_ZHIE = 0x20,
426 
427  LIS3DH_INT2_CFG_6D = 0x40,
428  LIS3DH_INT2_CFG_AOI = 0x80,
429 } LIS3DH_INT2_CFG_BITS_T;
430 
434 typedef enum {
435  LIS3DH_INT2_SRC_XL = 0x01,
436  LIS3DH_INT2_SRC_XH = 0x02,
437 
438  LIS3DH_INT2_SRC_YL = 0x04,
439  LIS3DH_INT2_SRC_YH = 0x08,
440 
441  LIS3DH_INT2_SRC_ZL = 0x10,
442  LIS3DH_INT2_SRC_ZH = 0x20,
443 
444  LIS3DH_INT2_SRC_IA = 0x40,
445 
446  // 0x80 reserved
447 } LIS3DH_INT2_SRC_BITS_T;
448 
452 typedef enum {
453  LIS3DH_CLICK_CFG_XS = 0x01,
454  LIS3DH_CLICK_CFG_XD = 0x02,
455 
456  LIS3DH_CLICK_CFG_YS = 0x04,
457  LIS3DH_CLICK_CFG_YD = 0x08,
458 
459  LIS3DH_CLICK_CFG_ZS = 0x10,
460  LIS3DH_CLICK_CFG_ZD = 0x20,
461 
462  // 0x40-0x80 reserved
463 } LIS3DH_CLICK_CFG_BITS_T;
464 
468 typedef enum {
469  LIS3DH_CLICK_SRC_X = 0x01,
470  LIS3DH_CLICK_SRC_Y = 0x02,
471  LIS3DH_CLICK_SRC_Z = 0x04,
472 
473  LIS3DH_CLICK_SRC_SIGN = 0x08,
474 
475  LIS3DH_CLICK_SRC_SCLICK = 0x10,
476  LIS3DH_CLICK_SRC_DCLICK = 0x20,
477 
478  LIS3DH_CLICK_SRC_IA = 0x40,
479 
480  // 0x80 reserved
481 } LIS3DH_CLICK_SRC_BITS_T;
482 
486 typedef enum {
487  LIS3DH_CLICK_THS_THS0 = 0x01,
488  LIS3DH_CLICK_THS_THS1 = 0x02,
489  LIS3DH_CLICK_THS_THS2 = 0x04,
490  LIS3DH_CLICK_THS_THS3 = 0x08,
491  LIS3DH_CLICK_THS_THS4 = 0x10,
492  LIS3DH_CLICK_THS_THS5 = 0x20,
493  LIS3DH_CLICK_THS_THS6 = 0x40,
494  _LIS3DH_CLICK_THS_THS_MASK = 0x7F, // 0b1111111
495  _LIS3DH_CLICK_THS_THS_SHIFT = 0,
496 
497  LIS3DH_CLICK_THS_LIR_CLICK = 0x80,
498 } LIS3DH_CLICK_THS_BITS_T;
499 
500 // Interrupt selection for installISR() and uninstallISR()
501 typedef enum { LIS3DH_INTERRUPT_INT1, LIS3DH_INTERRUPT_INT2 } LIS3DH_INTERRUPT_PINS_T;
502 
503 #ifdef __cplusplus
504 }
505 #endif