36 #include <sys/select.h>
37 #include <sys/types.h>
41 #include <mraa/common.hpp>
42 #include <mraa/spi.hpp>
43 #include <mraa/gpio.hpp>
87 static const uint8_t chipRevision = 0x12;
90 static const double FXOSC_FREQ = 32000000.0;
94 static const double FXOSC_STEP = 61.03515625;
97 static const int FIFO_SIZE = 256;
100 static const int RF_MID_BAND_THRESH = 525000000;
103 static const int LOR_RSSI_OFFSET_HF = -157;
104 static const int LOR_RSSI_OFFSET_LF = -164;
148 COM_RegOpMode = 0x01,
150 FSK_RegBitrateMsb = 0x02,
151 LOR_Reserved02 = 0x02,
153 FSK_RegBitrateLsb = 0x03,
154 LOR_Reserved03 = 0x03,
156 FSK_RegFdevMsb = 0x04,
157 LOR_Reserved04 = 0x04,
159 FSK_RegFdevLsb = 0x05,
160 LOR_Reserved05 = 0x05,
162 COM_RegFrfMsb = 0x06,
163 COM_RegFrfMid = 0x07,
164 COM_RegFrfLsb = 0x08,
165 COM_RegPaConfig = 0x09,
166 COM_RegPaRamp = 0x0a,
171 FSK_RegRxConfig = 0x0d,
172 LOR_RegFifoAddrPtr = 0x0d,
174 FSK_RegRssiConfg = 0x0e,
175 LOR_RegFifoTxBaseAddr = 0x0e,
177 FSK_RegRssiCollision = 0x0f,
178 LOR_RegFifoRxBaseAddr = 0x0f,
180 FSK_RegRssiThresh = 0x10,
181 LOR_RegFifoRxCurrentAddr = 0x10,
183 FSK_RegRssiValue = 0x11,
184 LOR_RegIrqFlagsMask = 0x11,
187 LOR_RegIrqFlags = 0x12,
190 LOR_RegRxNbBytes = 0x13,
192 FSK_RegOokPeak = 0x14,
193 LOR_RegRxHeaderCntValueMsb = 0x14,
195 FSK_RegOokFix = 0x15,
196 LOR_RegRxHeaderCntValueLsb = 0x15,
198 FSK_RegOokAvg = 0x16,
199 LOR_RegRxPacketCntValueMsb = 0x16,
201 FSK_Reserved17 = 0x17,
202 LOR_RegRxPacketCntValueLsb = 0x17,
204 FSK_Reserved18 = 0x18,
205 LOR_RegModemStat = 0x18,
207 FSK_Reserved19 = 0x19,
208 LOR_RegPktSnrValue = 0x19,
210 FSK_RegAfcFei = 0x1a,
211 LOR_RegPktRssiValue = 0x1a,
213 FSK_RegAfcMsb = 0x1b,
214 LOR_RegRssiValue = 0x1b,
216 FSK_RegAfcLsb = 0x1c,
217 LOR_RegHopChannel = 0x1c,
219 FSK_RegFeiMsb = 0x1d,
220 LOR_RegModemConfig1 = 0x1d,
222 FSK_RegFeiLsb = 0x1e,
223 LOR_RegModemConfig2 = 0x1e,
225 FSK_RegPreambleDetect = 0x1f,
226 LOR_RegSymbTimeoutLsb = 0x1f,
228 FSK_RegRxTimeout1 = 0x20,
229 LOR_RegPreambleMsb = 0x20,
231 FSK_RegRxTimeout2 = 0x21,
232 LOR_RegPreambleLsb = 0x21,
234 FSK_RegRxTimeout3 = 0x22,
235 LOR_RegPayloadLength = 0x22,
237 FSK_RegRxDelay = 0x23,
238 LOR_RegMaxPayloadLength = 0x23,
241 LOR_RegHopPeriod = 0x24,
243 FSK_RegPreambleMsb = 0x25,
244 LOR_RegFifoRxByteAddr = 0x25,
246 FSK_RegPreambleLsb = 0x26,
247 LOR_RegModemConfig3 = 0x26,
249 FSK_RegSyncConfig = 0x27,
250 LOR_Reserved27 = 0x27,
252 FSK_RegSyncValue1 = 0x28,
253 LOR_RegFeiMsb = 0x28,
255 FSK_RegSyncValue2 = 0x29,
256 LOR_RegFeiMid = 0x29,
258 FSK_RegSyncValue3 = 0x2a,
259 LOR_RegFeiLsb = 0x2a,
261 FSK_RegSyncValue4 = 0x2b,
262 LOR_Reserved2b = 0x2b,
264 FSK_RegSyncValue5 = 0x2c,
265 LOR_RegRssiWideband = 0x2c,
267 FSK_RegSyncValue6 = 0x2d,
268 LOR_Reserved2d = 0x2d,
270 FSK_RegSyncValue7 = 0x2e,
271 LOR_Reserved2e = 0x2e,
273 FSK_RegSyncValue8 = 0x2f,
274 LOR_Reserved2f = 0x2f,
276 FSK_RegPacketConfig1 = 0x30,
277 LOR_Reserved30 = 0x30,
279 FSK_RegPacketConfig2 = 0x31,
280 LOR_RegDetectOptimize = 0x31,
282 FSK_RegPayloadLength = 0x32,
283 LOR_Reserved32 = 0x32,
285 FSK_RegNodeAddr = 0x33,
286 LOR_RegInvertIQ = 0x33,
288 FSK_RegBroadcastAddr = 0x34,
289 LOR_Reserved34 = 0x34,
291 FSK_RegFifoThresh = 0x35,
292 LOR_Reserved35 = 0x35,
294 FSK_RegSeqConfig1 = 0x36,
295 LOR_Reserved36 = 0x36,
297 FSK_RegSeqConfig2 = 0x37,
298 LOR_RegDetectionThreshold = 0x37,
300 FSK_RegTimerResol = 0x38,
301 LOR_Reserved38 = 0x38,
303 FSK_RegTimer1Coeff = 0x39,
304 LOR_RegSyncWord = 0x39,
306 FSK_RegTimer2Coeff = 0x3a,
307 LOR_Reserved3a = 0x3a,
309 FSK_RegImageCal = 0x3b,
310 LOR_Reserved3b = 0x3b,
311 LOR_RegInvertIQ2 = 0x3b,
316 LOR_Reserved3c = 0x3c,
318 FSK_RegLowBat = 0x3d,
319 LOR_Reserved3d = 0x3d,
321 FSK_RegIrqFlags1 = 0x3e,
322 LOR_Reserved3e = 0x3e,
324 FSK_RegIrqFlags2 = 0x3f,
325 LOR_Reserved3f = 0x3f,
327 COM_RegDioMapping1 = 0x40,
328 COM_RegDioMapping2 = 0x41,
330 COM_RegVersion = 0x42,
341 FSK_Reserved44 = 0x44,
342 LOR_RegPllHop = 0x44,
354 COM_RegFormerTemp = 0x5b,
358 FSK_RegBitRateFrac = 0x5d,
359 LOR_Reserved5d = 0x5d,
363 COM_RegAgcRef = 0x61,
364 COM_RegAgcThresh1 = 0x62,
365 COM_RegAgcThresh2 = 0x63,
366 COM_RegAgcThresh3 = 0x64,
382 _OPMODE_Mode_MASK = 7,
383 _OPMODE_Mode_SHIFT = 0,
385 OPMODE_LowFrequencyModeOn = 0x08,
389 OPMODE_FSK_ModulationType0 = 0x20,
390 OPMODE_FSK_ModulationType1 = 0x40,
391 _OPMODE_FSK_ModulationType_MASK = 3,
392 _OPMODE_FSK_ModulationType_SHIFT = 5,
394 OPMODE_LOR_Reserved0x20 = 0x20,
396 OPMODE_LOR_AccessSharedReg = 0x40,
398 OPMODE_LongRangeMode = 0x80
413 MODE_LOR_RxContinuous = 5,
415 MODE_FSK_Reserved6 = 6,
416 MODE_LOR_RxSingle = 6,
418 MODE_FSK_Reserved7 = 7,
435 PACONFIG_OutputPower0 = 0x01,
436 PACONFIG_OutputPower1 = 0x02,
437 PACONFIG_OutputPower2 = 0x04,
438 PACONFIG_OutputPower3 = 0x08,
439 _PACONFIG_OutputPower_MASK = 15,
440 _PACONFIG_OutputPower_SHIFT = 0,
442 PACONFIG_MaxPower0 = 0x10,
443 PACONFIG_MaxPower1 = 0x20,
444 PACONFIG_MaxPower2 = 0x40,
445 _PACONFIG_MaxPower_MASK = 7,
446 _PACONFIG_MaxPower_SHIFT = 4,
448 PACONFIG_PaSelect = 0x80
456 PARAMP_PaRamp0 = 0x01,
457 PARAMP_PaRamp1 = 0x02,
458 PARAMP_PaRamp2 = 0x04,
459 PARAMP_PaRamp3 = 0x08,
460 _PARAMP_PaRamp_MASK = 15,
461 _PARAMP_PaRamp_SHIFT = 0,
467 PARAMP_FSK_ModulationShaping0 = 0x20,
468 PARAMP_FSK_ModulationShaping1 = 0x40,
469 _PARAMP_FSK_ModulationShaping_MASK = 3,
470 _PARAMP_FSK_ModulationShaping_SHIFT = 5
504 MODSHAPING_NOSHAPING = 0,
507 MODSHAPING_FSK_GaussianFilterBT1 = 1,
508 MODSHAPING_FSK_GaussianFilterBT05 = 2,
509 MODSHAPING_FSK_GaussianFilterBT03 = 3,
512 MODSHAPING_OOK_FCutoffBitRate = 1,
513 MODSHAPING_OOK_FCutoffBitRate2 = 2
526 _OCP_OcpTrim_MASK = 15,
527 _OCP_OcpTrim_SHIFT = 0,
538 LNA_LnaBoostHf0 = 0x01,
539 LNA_LnaBoostHf1 = 0x02,
540 _LNA_LnaBoostHf_MASK = 3,
541 _LNA_LnaBoostHf_SHIFT = 0,
545 LNA_LnaBoostLf0 = 0x08,
546 LNA_LnaBoostLf1 = 0x10,
547 _LNA_LnaBoostLf_MASK = 3,
548 _LNA_LnaBoostLf_SHIFT = 3,
553 _LNA_LnaGain_MASK = 7,
554 _LNA_LnaGain_SHIFT = 5
561 LNABOOSTHF_Default = 0,
563 LNABOOSTHF_BoostOn = 3,
570 LNABOOSTLF_Default = 0
593 RXCONFIG_RxTrigger0 = 0x01,
594 RXCONFIG_RxTrigger1 = 0x02,
595 RXCONFIG_RxTrigger2 = 0x04,
596 _RXCONFIG_RxTrigger_MASK = 7,
597 _RXCONFIG_RxTrigger_SHIFT = 0,
599 RXCONFIG_AgcAutoOn = 0x08,
600 RXCONFIG_AfcAutoOn = 0x10,
601 RXCONFIG_RestartRxWithPllLock = 0x20,
602 RXCONFIG_RestartRxWithoutPllLock = 0x40,
603 RXCONFIG_RestartRxOnCollision = 0x80
610 RSSICONFIG_RssiSmoothing0 = 0x01,
611 RSSICONFIG_RssiSmoothing1 = 0x02,
612 RSSICONFIG_RssiSmoothing2 = 0x04,
613 _RSSICONFIG_RssiSmoothing_MASK = 7,
614 _RSSICONFIG_RssiSmoothing_SHIFT = 0,
616 RSSICONFIG_RssiOffset0 = 0x08,
617 RSSICONFIG_RssiOffset1 = 0x10,
618 RSSICONFIG_RssiOffset2 = 0x20,
619 RSSICONFIG_RssiOffset3 = 0x40,
620 RSSICONFIG_RssiOffset4 = 0x80,
621 _RSSICONFIG_RssiOffset_MASK = 31,
622 _RSSICONFIG_RssiOffset_SHIFT = 3
632 RSSISMOOTHING_16 = 3,
633 RSSISMOOTHING_32 = 4,
634 RSSISMOOTHING_64 = 5,
635 RSSISMOOTHING_128 = 6,
636 RSSISMOOTHING_256 = 7
643 LOR_IRQFLAG_CadDetected = 0x01,
644 LOR_IRQFLAG_FhssChangeChannel = 0x02,
645 LOR_IRQFLAG_CadDone = 0x04,
646 LOR_IRQFLAG_TxDone = 0x08,
648 LOR_IRQFLAG_ValidHeader = 0x10,
649 LOR_IRQFLAG_PayloadCrcError = 0x20,
650 LOR_IRQFLAG_RxDone = 0x40,
651 LOR_IRQFLAG_RxTimeout = 0x80
658 RXBW_RxBwExp0 = 0x01,
659 RXBW_RxBwExp1 = 0x02,
660 RXBW_RxBwExp2 = 0x04,
661 _RXBW_RxBwExp_MASK = 7,
662 _RXBW_RxBwExp_SHIFT = 0,
664 RXBW_RxBwMant0 = 0x08,
665 RXBW_RxBwMant1 = 0x10,
666 _RXBW_RxBwMant_MASK = 3,
667 _RXBW_RxBwMant_SHIFT = 3,
699 OOKPEAK_OokPeakThreshStep0 = 0x01,
700 OOKPEAK_OokPeakThreshStep1 = 0x02,
701 OOKPEAK_OokPeakThreshStep2 = 0x04,
702 _OOKPEAK_OokPeakThreshStep_MASK = 7,
703 _OOKPEAK_OokPeakThreshStep_SHIFT = 0,
705 OOKPEAK_OokThreshType0 = 0x08,
706 OOKPEAK_OokThreshType1 = 0x10,
707 _OOKPEAK_OokThreshType_MASK = 3,
708 _OOKPEAK_OokThreshType_SHIFT = 3,
710 OOKPEAK_BitSyncOn = 0x20,
719 OOKPEAKTHRESHSTEP_05dB = 0,
720 OOKPEAKTHRESHSTEP_1dB = 1,
721 OOKPEAKTHRESHSTEP_15dB = 2,
722 OOKPEAKTHRESHSTEP_2dB = 3,
723 OOKPEAKTHRESHSTEP_3dB = 4,
724 OOKPEAKTHRESHSTEP_4dB = 5,
725 OOKPEAKTHRESHSTEP_5dB = 6,
726 OOKPEAKTHRESHSTEP_6dB = 7
733 OOKTHRESHTYPE_FIXED = 0,
734 OOKTHRESHTYPE_PEAK = 1,
735 OOKTHRESHTYPE_AVERAGE = 2
743 OOKAVG_OokAvgThreshFilt0 = 0x01,
744 OOKAVG_OokAvgThreshFilt1 = 0x02,
745 _OOKAVG_OokAvgThreshFilt_MASK = 3,
746 _OOKAVG_OokAvgThreshFilt_SHIFT = 0,
748 OOKAVG_OokAvgOffset0 = 0x04,
749 OOKAVG_OokAvgOffset1 = 0x08,
750 _OOKAVG_OokAvgOffset_MASK = 3,
751 _OOKAVG_OokAvgOffset_SHIFT = 2,
755 OOKAVG_OokPeakThreshDec0 = 0x20,
756 OOKAVG_OokPeakThreshDec1 = 0x40,
757 OOKAVG_OokPeakThreshDec2 = 0x80,
758 _OOKAVG_OokPeakThreshDec_MASK = 7,
759 _OOKAVG_OokPeakThreshDec_SHIFT = 5
766 OOKAVGTHRESHFILT_32 = 0,
767 OOKAVGTHRESHFILT_8 = 1,
768 OOKAVGTHRESHFILT_4 = 2,
769 OOKAVGTHRESHFILT_2 = 3
786 OOKPEAKTHRESHDEC_1_1 = 0,
787 OOKPEAKTHRESHDEC_1_2 = 1,
788 OOKPEAKTHRESHDEC_1_4 = 2,
789 OOKPEAKTHRESHDEC_1_8 = 3,
790 OOKPEAKTHRESHDEC_2_1 = 4,
791 OOKPEAKTHRESHDEC_4_1 = 5,
792 OOKPEAKTHRESHDEC_8_1 = 6,
793 OOKPEAKTHRESHDEC_16_1 = 7
800 MODEMSTAT_SignalDetected = 0x01,
801 MODEMSTAT_SignalSynchronized = 0x02,
802 MODEMSTAT_RxOngoing = 0x04,
803 MODEMSTAT_HeaderInfoValid = 0x08,
804 MODEMSTAT_ModemClear = 0x10,
806 MODEMSTAT_RxCodingRate0 = 0x20,
807 MODEMSTAT_RxCodingRate1 = 0x40,
808 MODEMSTAT_RxCodingRate2 = 0x80,
809 _MODEMSTAT_RxCodingRate_MASK = 7,
810 _MODEMSTAT_RxCodingRate_SHIFT = 5
817 AFCFEI_AfcAutoClearOn = 0x01,
818 AFCFEI_AfcClear = 0x02,
822 AFCFEI_AgcStart = 0x10
831 HOPCHANNEL_FhssPresentChannel0 = 0x01,
832 HOPCHANNEL_FhssPresentChannel1 = 0x02,
833 HOPCHANNEL_FhssPresentChannel2 = 0x04,
834 HOPCHANNEL_FhssPresentChannel3 = 0x08,
835 HOPCHANNEL_FhssPresentChannel4 = 0x10,
836 HOPCHANNEL_FhssPresentChannel5 = 0x20,
837 _HOPCHANNEL_FhssPresentChannel_MASK = 63,
838 _HOPCHANNEL_FhssPresentChannel_SHIFT = 0,
840 HOPCHANNEL_CrcOnPayload = 0x40,
841 HOPCHANNEL_PllTimeout = 0x80
848 MODEMCONFIG1_ImplicitHeaderModeOn = 0x01,
850 MODEMCONFIG1_CodingRate0 = 0x02,
851 MODEMCONFIG1_CodingRate1 = 0x04,
852 MODEMCONFIG1_CodingRate2 = 0x08,
853 _MODEMCONFIG1_CodingRate_MASK = 7,
854 _MODEMCONFIG1_CodingRate_SHIFT = 0,
856 MODEMCONFIG1_Bw0 = 0x10,
857 MODEMCONFIG1_Bw1 = 0x20,
858 MODEMCONFIG1_Bw2 = 0x40,
859 MODEMCONFIG1_Bw3 = 0x80,
860 _MODEMCONFIG1_Bw_MASK = 15,
861 _MODEMCONFIG1_Bw_SHIFT = 4
896 MODEMCONFIG2_SymbTimeoutMsb0 = 0x01,
897 MODEMCONFIG2_SymbTimeoutMsb1 = 0x02,
898 _MODEMCONFIG2_SymbTimeoutMsb_MASK = 3,
899 _MODEMCONFIG2_SymbTimeoutMsb_SHIFT = 0,
901 MODEMCONFIG2_RxPayloadCrcOn = 0x04,
903 MODEMCONFIG2_TxContinuousMode = 0x08,
905 MODEMCONFIG2_SpreadingFactor0 = 0x10,
906 MODEMCONFIG2_SpreadingFactor1 = 0x20,
907 MODEMCONFIG2_SpreadingFactor2 = 0x40,
908 MODEMCONFIG2_SpreadingFactor3 = 0x80,
909 _MODEMCONFIG2_SpreadingFactor_MASK = 15,
910 _MODEMCONFIG2_SpreadingFactor_SHIFT = 4,
917 SPREADINGFACTOR_64 = 6,
918 SPREADINGFACTOR_128 = 7,
919 SPREADINGFACTOR_256 = 8,
920 SPREADINGFACTOR_512 = 9,
921 SPREADINGFACTOR_1024 = 10,
922 SPREADINGFACTOR_2048 = 11,
923 SPREADINGFACTOR_4096 = 12
932 PREABLEDETECT_PreambleDetectorTol0 = 0x01,
933 PREABLEDETECT_PreambleDetectorTol1 = 0x02,
934 PREABLEDETECT_PreambleDetectorTol2 = 0x04,
935 PREABLEDETECT_PreambleDetectorTol3 = 0x08,
936 PREABLEDETECT_PreambleDetectorTol4 = 0x10,
937 _PREABLEDETECT_PreambleDetectorTol4_MASK = 31,
938 _PREABLEDETECT_PreambleDetectorTol4_SHIFT = 0,
940 PREABLEDETECT_PreambleDetectorSize0 = 0x20,
941 PREABLEDETECT_PreambleDetectorSize1 = 0x40,
942 _PREABLEDETECT_PreambleDetectorSize_MASK = 3,
943 _PREABLEDETECT_PreambleDetectorSize_SHIFT = 5,
945 PREABLEDETECT_PreambleDetectorOn = 0x80
952 PREAMBLEDETECTORSIZE_1 = 0,
953 PREAMBLEDETECTORSIZE_2 = 1,
954 PREAMBLEDETECTORSIZE_3 = 2
966 _OSC_ClkOut_MASK = 7,
967 _OSC_ClkOut_SHIFT = 0,
969 OSC_RcCalStart = 0x08
994 MODEMCONFIG3_AgcAutoOn = 0x04,
995 MODEMCONFIG3_LowDataRateOptimize = 0x08
1005 SYNCCONFIG_SyncSize0 = 0x01,
1006 SYNCCONFIG_SyncSize1 = 0x02,
1007 SYNCCONFIG_SyncSize2 = 0x04,
1008 _SYNCCONFIG_SyncSize_MASK = 7,
1009 _SYNCCONFIG_SyncSize_SHIFT = 0,
1013 SYNCCONFIG_SyncOn = 0x10,
1014 SYNCCONFIG_PreamblePolarity = 0x20,
1016 SYNCCONFIG_AutoRestartMode0 = 0x40,
1017 SYNCCONFIG_AutoRestartMode1 = 0x80,
1018 _SYNCCONFIG_AutoRestartMode_MASK = 3,
1019 _SYNCCONFIG_AutoRestartMode_SHIFT = 6,
1026 AUTORESTARTMODE_OFF = 0,
1027 AUTORESTARTMODE_ON_NOPLL = 1,
1028 AUTORESTARTMODE_ON_PLL = 2
1036 FEIMSB_FreqError0 = 0x01,
1037 FEIMSB_FreqError1 = 0x02,
1038 FEIMSB_FreqError2 = 0x04,
1039 FEIMSB_FreqError3 = 0x08,
1040 _FEIMSB_FreqError_MASK = 15,
1041 _FEIMSB_FreqError_SHIFT = 0
1050 PACKETCONFIG1_CrcWhiteningType = 0x01,
1052 PACKETCONFIG1_AddressFiltering0 = 0x02,
1053 PACKETCONFIG1_AddressFiltering1 = 0x04,
1054 _PACKETCONFIG1_AddressFiltering_MASK = 3,
1055 _PACKETCONFIG1_AddressFiltering_SHIFT = 1,
1057 PACKETCONFIG1_CrcAutoClearOff = 0x08,
1058 PACKETCONFIG1_CrcOn = 0x10,
1060 PACKETCONFIG1_DcFree0 = 0x20,
1061 PACKETCONFIG1_DcFree1 = 0x40,
1062 _PACKETCONFIG1_DcFree_MASK = 3,
1063 _PACKETCONFIG1_DcFree_SHIFT = 5,
1065 PACKETCONFIG1_PacketFormat = 0x80
1072 ADDRESSFILTERING_NONE = 0,
1073 ADDRESSFILTERING_NODE = 1,
1074 ADDRESSFILTERING_NODE_BROADCAST = 2,
1082 DCFREE_MANCHESTER = 1,
1083 DCFREE_WHITENING = 2
1091 PACKETCONFIG2_PayloadLengthMsb0 = 0x01,
1092 PACKETCONFIG2_PayloadLengthMsb1 = 0x02,
1093 PACKETCONFIG2_PayloadLengthMsb2 = 0x04,
1094 _PACKETCONFIG2_PayloadLengthMsb_MASK = 7,
1095 _PACKETCONFIG2_PayloadLengthMsb_SHIFT = 0,
1097 PACKETCONFIG2_BeaconOn = 0x08,
1101 PACKETCONFIG2_IoHomeOn = 0x20,
1102 PACKETCONFIG2_DataMode = 0x40,
1111 DETECTOPTIMIZE_DetectionOptimize0 = 0x01,
1112 DETECTOPTIMIZE_DetectionOptimize1 = 0x02,
1113 DETECTOPTIMIZE_DetectionOptimize2 = 0x04,
1114 _DETECTOPTIMIZE_DetectionOptimize_MASK = 7,
1115 _DETECTOPTIMIZE_DetectionOptimize_SHIFT = 0
1124 DETECTIONOPTIMIZE_SF7_SF12 = 3,
1125 DETECTIONOPTIMIZE_SF6 = 5
1134 INVERTIQ_InvertIQTxOff = 0x01,
1139 INVERTIQ_InvertIQRx = 0x40
1148 FIFOTHRESH_FifoThreshold0 = 0x01,
1149 FIFOTHRESH_FifoThreshold1 = 0x02,
1150 FIFOTHRESH_FifoThreshold2 = 0x04,
1151 FIFOTHRESH_FifoThreshold3 = 0x08,
1152 FIFOTHRESH_FifoThreshold4 = 0x10,
1153 FIFOTHRESH_FifoThreshold5 = 0x20,
1154 _FIFOTHRESH_FifoThreshold_MASK = 63,
1155 _FIFOTHRESH_FifoThreshold_SHIFT = 0,
1159 FIFOTHRESH_TxStartCondition = 0x80
1166 SEQCONFIG1_FromTransit = 0x01,
1167 SEQCONFIG1_FromIdle = 0x02,
1168 SEQCONFIG1_LowPowerSelection = 0x04,
1170 SEQCONFIG1_FromStart0 = 0x08,
1171 SEQCONFIG1_FromStart1 = 0x10,
1172 _SEQCONFIG1_FromStart_MASK = 3,
1173 _SEQCONFIG1_FromStart_SHIFT = 3,
1175 SEQCONFIG1_IdleMode = 0x20,
1176 SEQCONFIG1_SequencerStop = 0x40,
1177 SEQCONFIG1_SequencerStart = 0x80
1184 FROMSTART_ToLowPowerSelection = 0,
1185 FROMSTART_ToReceiveState = 1,
1186 FROMSTART_ToTransmitState = 2,
1187 FROMSTART_ToTransmitStateOnFifoLevel = 3
1194 SEQCONFIG2_FromPacketReceived0 = 0x01,
1195 SEQCONFIG2_FromPacketReceived1 = 0x02,
1196 SEQCONFIG2_FromPacketReceived2 = 0x04,
1197 _SEQCONFIG2_FromPacketReceived_MASK = 7,
1198 _SEQCONFIG2_FromPacketReceived_SHIFT = 0,
1200 SEQCONFIG2_FromRxTimeout0 = 0x08,
1201 SEQCONFIG2_FromRxTimeout1 = 0x10,
1202 _SEQCONFIG2_FromRxTimeout_MASK = 3,
1203 _SEQCONFIG2_FromRxTimeout_SHIFT = 3,
1205 SEQCONFIG2_FromReceive0 = 0x20,
1206 SEQCONFIG2_FromReceive1 = 0x40,
1207 SEQCONFIG2_FromReceive2 = 0x80,
1208 _SEQCONFIG2_FromReceive_MASK = 3,
1209 _SEQCONFIG2_FromReceive_SHIFT = 5
1216 FROMPACKETRECEIVED_ToSequencerOff = 0,
1217 FROMPACKETRECEIVED_ToTransmitStateOnFifoEmpty = 1,
1218 FROMPACKETRECEIVED_ToLowPowerSelection = 2,
1219 FROMPACKETRECEIVED_ToReceiveViaFS = 3,
1220 FROMPACKETRECEIVED_ToReceive = 4
1229 FROMRXTIMEOUT_ToReceiveViaReceiveStart = 0,
1230 FROMRXTIMEOUT_ToTransmitState = 1,
1231 FROMRXTIMEOUT_ToLowPowerSelection = 2,
1232 FROMRXTIMEOUT_ToSequencerOffState = 3
1239 FROMRECEIVE_ToPcketReceived = 1,
1240 FROMRECEIVE_ToLowPowerSelection = 2,
1241 FROMRECEIVE_ToPacketReceived = 3,
1242 FROMRECEIVE_ToSequencerOffOnRSSI = 4,
1243 FROMRECEIVE_ToSequencerOffOnSync = 5,
1244 FROMRECEIVE_ToSequencerOffOnPreambleDetect = 6,
1252 TIMERRESOL_Timer2Resolution0 = 0x01,
1253 TIMERRESOL_Timer2Resolution1 = 0x02,
1254 _TIMERRESOL_Timer2Resolution_MASK = 3,
1255 _TIMERRESOL_Timer2Resolution_SHIFT = 0,
1257 TIMERRESOL_Timer1Resolution0 = 0x04,
1258 TIMERRESOL_Timer1Resolution1 = 0x08,
1259 _TIMERRESOL_Timer1Resolution_MASK = 3,
1260 _TIMERRESOL_Timer1Resolution_SHIFT = 2
1269 TIMERRESOLUTION_DISABLED = 0,
1270 TIMERRESOLUTION_64us = 1,
1271 TIMERRESOLUTION_4_1ms = 2,
1272 TIMERRESOLUTION_262ms = 3
1279 IMAGECAL_TempMonitorOff = 0x01,
1281 IMAGECAL_TempThreshold0 = 0x02,
1282 IMAGECAL_TempThreshold1 = 0x04,
1283 _IMAGECAL_TempThreshold_MASK = 3,
1284 _IMAGECAL_TempThreshold_SHIFT = 1,
1286 IMAGECAL_TenpChange = 0x08,
1290 IMAGECAL_ImageCalRunning = 0x20,
1291 IMAGECAL_ImageCalStart = 0x40,
1292 IMAGECAL_AutoImageCalOn = 0x80
1299 TEMPTHRESHOLD_5C = 0,
1300 TEMPTHRESHOLD_10C = 1,
1301 TEMPTHRESHOLD_15C = 2,
1302 TEMPTHRESHOLD_20C = 3
1309 LOWBAT_LowBatTrim0 = 0x01,
1310 LOWBAT_LowBatTrim1 = 0x02,
1311 LOWBAT_LowBatTrim2 = 0x04,
1312 _LOWBAT_LowBatTrim_MASK = 7,
1313 _LOWBAT_LowBatTrim_SHIFT = 0,
1315 LOWBAT_LowBatOn = 0x08
1324 LOWBATTRIM_1_695 = 0,
1325 LOWBATTRIM_1_764 = 1,
1326 LOWBATTRIM_1_835 = 2,
1327 LOWBATTRIM_1_905 = 3,
1328 LOWBATTRIM_1_976 = 4,
1329 LOWBATTRIM_2_045 = 5,
1330 LOWBATTRIM_2_116 = 6,
1331 LOWBATTRIM_2_185 = 7
1338 IRQFLAGS1_SyncAddressMatch = 0x01,
1339 IRQFLAGS1_PreambleDetect = 0x02,
1340 IRQFLAGS1_Timeout = 0x04,
1341 IRQFLAGS1_Rssi = 0x08,
1342 IRQFLAGS1_PllLock = 0x10,
1343 IRQFLAGS1_TxReady = 0x20,
1344 IRQFLAGS1_RxReady = 0x40,
1345 IRQFLAGS1_ModeReady = 0x80
1352 IRQFLAGS2_LowBat = 0x01,
1353 IRQFLAGS2_CrcOk = 0x02,
1354 IRQFLAGS2_PayloadReady = 0x04,
1355 IRQFLAGS2_PacketSent = 0x08,
1356 IRQFLAGS2_FifoOverrun = 0x10,
1357 IRQFLAGS2_FifoLevel = 0x20,
1358 IRQFLAGS2_FifoEmpty = 0x40,
1359 IRQFLAGS2_FifoFull = 0x80
1367 DOIMAPPING1_Dio3Mapping0 = 0x01,
1368 DOIMAPPING1_Dio3Mapping1 = 0x02,
1369 DOIMAPPING1_Dio3Mapping_MASK = 3,
1370 DOIMAPPING1_Dio3Mapping_SHIFT = 0,
1372 DOIMAPPING1_Dio2Mapping0 = 0x04,
1373 DOIMAPPING1_Dio2Mapping1 = 0x08,
1374 DOIMAPPING1_Dio2Mapping_MASK = 3,
1375 DOIMAPPING1_Dio2Mapping_SHIFT = 2,
1377 DOIMAPPING1_Dio1Mapping0 = 0x10,
1378 DOIMAPPING1_Dio1Mapping1 = 0x20,
1379 DOIMAPPING1_Dio1Mapping_MASK = 3,
1380 DOIMAPPING1_Dio1Mapping_SHIFT = 4,
1382 DOIMAPPING1_Dio0Mapping0 = 0x40,
1383 DOIMAPPING1_Dio0Mapping1 = 0x80,
1384 DOIMAPPING1_Dio0Mapping_MASK = 3,
1385 DOIMAPPING1_Dio0Mapping_SHIFT = 6,
1394 DOIMAPPING2_MapPreambleDetect = 0x01,
1398 DOIMAPPING2_Dio5Mapping0 = 0x10,
1399 DOIMAPPING2_Dio5Mapping1 = 0x20,
1400 DOIMAPPING2_Dio5Mapping_MASK = 3,
1401 DOIMAPPING2_Dio5Mapping_SHIFT = 4,
1403 DOIMAPPING2_Dio4Mapping0 = 0x40,
1404 DOIMAPPING2_Dio4Mapping1 = 0x80,
1405 DOIMAPPING2_Dio4Mapping_MASK = 3,
1406 DOIMAPPING2_Dio4Mapping_SHIFT = 6,
1430 PLLHOP_FastHopOn = 0x80
1448 PADAC_PaDac0 = 0x01,
1449 PADAC_PaDac1 = 0x02,
1450 PADAC_PaDac2 = 0x04,
1451 _PADAC_PaDac_MASK = 7,
1452 _PADAC_PaDac_SHIFT = 0
1471 BITRATEFRAC_BitRateFrac0 = 0x01,
1472 BITRATEFRAC_BitRateFrac1 = 0x02,
1473 BITRATEFRAC_BitRateFrac2 = 0x04,
1474 BITRATEFRAC_BitRateFrac3 = 0x08,
1475 _BITRATEFRAC_BitRateFrac_MASK = 15,
1476 _BITRATEFRAC_BitRateFrac_SHIFT = 0
1488 AGCREF_AgcReferenceLevel0 = 0x01,
1489 AGCREF_AgcReferenceLevel1 = 0x02,
1490 AGCREF_AgcReferenceLevel2 = 0x04,
1491 AGCREF_AgcReferenceLevel3 = 0x08,
1492 AGCREF_AgcReferenceLevel4 = 0x10,
1493 AGCREF_AgcReferenceLevel5 = 0x20,
1494 _AGCREF_AgcReferenceLevel_MASK = 63,
1495 _AGCREF_AgcReferenceLevel_SHIFT = 0
1507 AGCTHRESH1_AcgStep10 = 0x01,
1508 AGCTHRESH1_AcgStep11 = 0x02,
1509 AGCTHRESH1_AcgStep12 = 0x04,
1510 AGCTHRESH1_AcgStep13 = 0x08,
1511 _AGCTHRESH1_AcgStep1_MASK = 15,
1512 _AGCTHRESH1_AcgStep1_SHIFT = 0,
1524 AGCTHRESH2_AcgStep30 = 0x01,
1525 AGCTHRESH2_AcgStep31 = 0x02,
1526 AGCTHRESH2_AcgStep32 = 0x04,
1527 AGCTHRESH2_AcgStep33 = 0x08,
1528 _AGCTHRESH2_AcgStep3_MASK = 15,
1529 _AGCTHRESH2_AcgStep3_SHIFT = 0,
1531 AGCTHRESH2_AcgStep20 = 0x10,
1532 AGCTHRESH2_AcgStep21 = 0x20,
1533 AGCTHRESH2_AcgStep22 = 0x40,
1534 AGCTHRESH2_AcgStep23 = 0x80,
1535 _AGCTHRESH2_AcgStep2_MASK = 15,
1536 _AGCTHRESH2_AcgStep2_SHIFT = 4
1543 LOR_DetectionThreshold_SF7_SF12 = 0x0a,
1544 LOR_DetectionThreshold_SF6 = 0x0c
1554 AGCTHRESH3_AcgStep50 = 0x01,
1555 AGCTHRESH3_AcgStep51 = 0x02,
1556 AGCTHRESH3_AcgStep52 = 0x04,
1557 AGCTHRESH3_AcgStep53 = 0x08,
1558 _AGCTHRESH3_AcgStep5_MASK = 15,
1559 _AGCTHRESH3_AcgStep5_SHIFT = 0,
1561 AGCTHRESH3_AcgStep40 = 0x10,
1562 AGCTHRESH3_AcgStep41 = 0x20,
1563 AGCTHRESH3_AcgStep42 = 0x40,
1564 AGCTHRESH3_AcgStep43 = 0x80,
1565 _AGCTHRESH3_AcgStep4_MASK = 15,
1566 _AGCTHRESH3_AcgStep4_SHIFT = 4
1587 SX1276(uint8_t chipRev=chipRevision,
int bus=1,
int cs=10,
int resetPin=14,
1588 int dio0=2,
int dio1=3,
int dio2=4,
int dio3=5,
int dio4=17,
1611 bool writeReg(uint8_t reg, uint8_t val);
1631 void readFifo(uint8_t *buffer,
int len);
1639 void writeFifo(uint8_t *buffer,
int len);
1757 uint32_t datarate, uint8_t coderate,
1758 uint32_t bandwidthAfc, uint16_t preambleLen,
1759 uint16_t symbTimeout,
bool fixLen,
1761 bool crcOn,
bool freqHopOn, uint8_t hopPeriod,
1762 bool iqInverted,
bool rxContinuous);
1802 uint32_t bandwidth, uint32_t datarate,
1803 uint8_t coderate, uint16_t preambleLen,
1804 bool fixLen,
bool crcOn,
bool freqHopOn,
1805 uint8_t hopPeriod,
bool iqInverted);
1827 std::string rBuffer((
char *)m_rxBuffer,
getRxLen());
1840 return (uint8_t*)m_rxBuffer;
1881 mraa::Gpio m_gpioCS;
1882 mraa::Gpio m_gpioReset;
1884 mraa::Gpio m_gpioDIO0;
1885 mraa::Gpio m_gpioDIO1;
1886 mraa::Gpio m_gpioDIO2;
1887 mraa::Gpio m_gpioDIO3;
1888 mraa::Gpio m_gpioDIO4;
1889 mraa::Gpio m_gpioDIO5;
1892 void rxChainCalibration();
1895 static void onDio0Irq(
void *ctx);
1896 static void onDio1Irq(
void *ctx);
1897 static void onDio2Irq(
void *ctx);
1898 static void onDio3Irq(
void *ctx);
1899 static void onDio4Irq(
void *ctx);
1900 static void onDio5Irq(
void *ctx);
1913 static const uint8_t m_writeMode = 0x80;
1948 uint32_t BandwidthAfc;
1950 uint16_t PreambleLen;
1956 } radioFskSettings_t;
1964 bool LowDatarateOptimize;
1966 uint16_t PreambleLen;
1974 } radioLoRaSettings_t;
1979 uint8_t PreambleDetected;
1980 uint8_t SyncWordDetected;
1988 } radioFskPacketHandler_t;
1996 } radioLoRaPacketHandler_t;
2004 radioFskSettings_t fskSettings;
2005 volatile radioFskPacketHandler_t fskPacketHandler;
2007 radioLoRaSettings_t loraSettings;
2008 volatile radioLoRaPacketHandler_t loraPacketHandler;
2011 uint8_t lookupFSKBandWidth(uint32_t bw);
2014 volatile int m_rxRSSI;
2015 volatile int m_rxSNR;
2016 volatile int m_rxLen;
2017 uint8_t m_rxBuffer[FIFO_SIZE];
2020 pthread_mutex_t m_intrLock;
2022 void lockIntrs() { pthread_mutex_lock(&m_intrLock); };
2023 void unlockIntrs() { pthread_mutex_unlock(&m_intrLock); };
2029 struct timeval m_startTime;
2031 uint32_t getMillis();
BW_T
Definition: sx1276.h:877
MODSHAPING_T
Definition: sx1276.h:503
SX1276(uint8_t chipRev=chipRevision, int bus=1, int cs=10, int resetPin=14, int dio0=2, int dio1=3, int dio2=4, int dio3=5, int dio4=17, int dio5=9)
Definition: sx1276.cxx:73
PARAMP_BITS_T
Definition: sx1276.h:455
OOKAVGOFFSET_T
Definition: sx1276.h:775
CODINGRATE_T
Definition: sx1276.h:867
LOWBATTRIM_T
Definition: sx1276.h:1323
RADIO_MODEM_T
Definition: sx1276.h:109
RADIO_EVENT_T
Definition: sx1276.h:127
RXCONFIG_BITS_T
Definition: sx1276.h:592
DCFREE_T
Definition: sx1276.h:1080
INVERTIQ_BITS_T
Definition: sx1276.h:1133
void readFifo(uint8_t *buffer, int len)
Definition: sx1276.cxx:198
void setRxConfig(RADIO_MODEM_T modem, uint32_t bandwidth, uint32_t datarate, uint8_t coderate, uint32_t bandwidthAfc, uint16_t preambleLen, uint16_t symbTimeout, bool fixLen, uint8_t payloadLen, bool crcOn, bool freqHopOn, uint8_t hopPeriod, bool iqInverted, bool rxContinuous)
Definition: sx1276.cxx:636
LNA_BITS_T
Definition: sx1276.h:537
PACKETCONFIG2_BITS_T
Definition: sx1276.h:1090
FSK_MODULATION_TYPE_T
Definition: sx1276.h:425
void setOpMode(MODE_T opMode)
Definition: sx1276.cxx:379
DETECTIONOPTIMIZE_T
Definition: sx1276.h:1123
MODEMSTAT_BITS_T
Definition: sx1276.h:799
SX1276_REGS_T
Definition: sx1276.h:146
~SX1276()
Definition: sx1276.cxx:159
PREAMBLEDETECTORSIZE_T
Definition: sx1276.h:951
MODEMCONFIG1_BITS_T
Definition: sx1276.h:847
RADIO_STATES_T
Definition: sx1276.h:1905
void writeFifo(uint8_t *buffer, int len)
Definition: sx1276.cxx:229
FROMRXTIMEOUT_T
Definition: sx1276.h:1228
FIFOTHRESH_BITS_T
Definition: sx1276.h:1147
OOKPEAK_BITS_T
Definition: sx1276.h:698
DIOMAPPING2_BITS_T
Definition: sx1276.h:1393
TIMERRESOLUTION_T
Definition: sx1276.h:1268
DIOMAPPING1_BITS_T
Definition: sx1276.h:1366
PARAMP_T
Definition: sx1276.h:478
LOR_IRQFLAG_BITS_T
Definition: sx1276.h:642
MODEMCONFIG3_BITS_T
Definition: sx1276.h:991
RADIO_EVENT_T send(uint8_t *buffer, uint8_t size, int timeout)
Definition: sx1276.cxx:547
RXBWEXP_T
Definition: sx1276.h:684
FROMRECEIVE_T
Definition: sx1276.h:1238
OOKAVGTHRESHFILT_T
Definition: sx1276.h:765
LNABOOSTLF_T
Definition: sx1276.h:569
void reset()
Definition: sx1276.cxx:267
MODE_T
Definition: sx1276.h:405
IRQFLAGS1_BITS_T
Definition: sx1276.h:1337
RSSISMOOTHING_T
Definition: sx1276.h:628
ACGTHRESH3_BITS_T
Definition: sx1276.h:1553
int getRxSNR()
Definition: sx1276.h:1861
void setChannel(uint32_t freq)
Definition: sx1276.cxx:368
LNAGAIN_T
Definition: sx1276.h:577
OPMODE_BITS_T
Definition: sx1276.h:378
void setTxConfig(RADIO_MODEM_T modem, int8_t power, uint32_t fdev, uint32_t bandwidth, uint32_t datarate, uint8_t coderate, uint16_t preambleLen, bool fixLen, bool crcOn, bool freqHopOn, uint8_t hopPeriod, bool iqInverted)
Definition: sx1276.cxx:884
SPREADINGFACTOR_T
Definition: sx1276.h:916
OOKTHRESHTYPE_T
Definition: sx1276.h:732
PLLHOP_BITS_T
Definition: sx1276.h:1427
DIOMAPPING_T
Definition: sx1276.h:1416
ACGTHRESH2_BITS_T
Definition: sx1276.h:1523
BITRATEFRAC_BITS_T
Definition: sx1276.h:1470
CLKOUT_T
Definition: sx1276.h:977
PADAC_T
Definition: sx1276.h:1460
LNABOOSTHF_T
Definition: sx1276.h:560
uint8_t getChipVersion()
Definition: sx1276.cxx:261
LOWBAT_BITS_T
Definition: sx1276.h:1308
SEQCONFIG2_BITS_T
Definition: sx1276.h:1193
IMAGECAL_BITS_T
Definition: sx1276.h:1278
PADAC_BITS_T
Definition: sx1276.h:1447
void setStandby()
Definition: sx1276.cxx:499
PACKETCONFIG1_BITS_T
Definition: sx1276.h:1049
bool isChannelFree(RADIO_MODEM_T modem, uint32_t freq, int16_t rssiThresh)
Definition: sx1276.cxx:433
TEMPTHRESHOLD_T
Definition: sx1276.h:1298
ADDRESSFILTERING_T
Definition: sx1276.h:1071
AUTORESTARTMODE_T
Definition: sx1276.h:1025
TCXO_BITS_T
Definition: sx1276.h:1436
FEIMSB_BITS_T
Definition: sx1276.h:1035
DETECTOPTIMIZE_BITS_T
Definition: sx1276.h:1110
void setModem(RADIO_MODEM_T modem)
Definition: sx1276.cxx:394
ACGTHRESH1_BITS_T
Definition: sx1276.h:1506
AFCFEI_BITS_T
Definition: sx1276.h:816
MODEMCONFIG2_BITS_T
Definition: sx1276.h:895
FROMSTART_T
Definition: sx1276.h:1183
std::string getRxBufferStr()
Definition: sx1276.h:1825
uint8_t * getRxBuffer()
Definition: sx1276.h:1838
IRQFLAGS2_BITS_T
Definition: sx1276.h:1351
OCP_BITS_T
Definition: sx1276.h:521
RXBW_BITS_T
Definition: sx1276.h:657
uint8_t readReg(uint8_t reg)
Definition: sx1276.cxx:164
ACFREF_BITS_T
Definition: sx1276.h:1487
int getRxRSSI()
Definition: sx1276.h:1850
PREAMBLEDETECT_BITS_T
Definition: sx1276.h:931
RADIO_EVENT_T setRx(uint32_t timeout)
Definition: sx1276.cxx:1273
LOR_DETECTIONTHRESHOLD_T
Definition: sx1276.h:1542
FROMPACKETRECEIVED_T
Definition: sx1276.h:1215
PACONFIG_BITS_T
Definition: sx1276.h:434
OOKPEAKTHRESHSTEP_T
Definition: sx1276.h:718
SYNCCONFIG_BITS_T
Definition: sx1276.h:1004
RADIO_EVENT_T sendStr(std::string buffer, int timeout)
Definition: sx1276.cxx:530
SEQCONFIG1_BITS_T
Definition: sx1276.h:1165
int16_t getRSSI(RADIO_MODEM_T modem)
Definition: sx1276.cxx:458
RSSICONFIG_BITS_T
Definition: sx1276.h:609
OOKAVG_BITS_T
Definition: sx1276.h:742
TIMERRESOL_BITS_T
Definition: sx1276.h:1251
bool writeReg(uint8_t reg, uint8_t val)
Definition: sx1276.cxx:181
int getRxLen()
Definition: sx1276.h:1872
RXBWMANT_T
Definition: sx1276.h:674
void setSleep()
Definition: sx1276.cxx:493
HOPCHANNEL_BITS_T
Definition: sx1276.h:830
API for the SX1276 LoRa/FSK modem.
Definition: sx1276.h:83
OSC_BITS_T
Definition: sx1276.h:962
OOKPEAKTHRESHDEC_T
Definition: sx1276.h:785