upm  1.7.1
Sensor/Actuator repository for libmraa (v2.0.0)
bmm150_defs.h
1 /*
2  * Author: Jon Trulson <jtrulson@ics.com>
3  * Copyright (c) 2017 Intel Corporation.
4  *
5  * The MIT License
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining
8  * a copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sublicense, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be
16  * included in all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
21  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26 #pragma once
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 #define BMM150_DEFAULT_I2C_BUS 0
33 #define BMM150_DEFAULT_SPI_BUS 0
34 #define BMM150_DEFAULT_ADDR 0x10
35 
36 #define BMM150_DEFAULT_CHIPID 0x32
37 
38  // NOTE: Reserved registers must not be written into. Reading
39  // from them may return indeterminate values. Registers
40  // containing reserved bitfields must be written as 0. Reading
41  // reserved bitfields may return indeterminate values.
42 
46  typedef enum {
47  BMM150_REG_CHIP_ID = 0x40,
48 
49  // 0x41 reserved
50 
51  BMM150_REG_MAG_X_LSB = 0x42,
52  BMM150_REG_MAG_X_MSB = 0x43,
53  BMM150_REG_MAG_Y_LSB = 0x44,
54  BMM150_REG_MAG_Y_MSB = 0x45,
55  BMM150_REG_MAG_Z_LSB = 0x46,
56  BMM150_REG_MAG_Z_MSB = 0x47,
57 
58  BMM150_REG_RHALL_LSB = 0x48,
59  BMM150_REG_RHALL_MSB = 0x49,
60 
61  BMM150_REG_INT_STATUS = 0x4a,
62 
63  BMM150_REG_POWER_CTRL = 0x4b,
64 
65  BMM150_REG_OPMODE = 0x4c,
66 
67  BMM150_REG_INT_EN = 0x4d,
68  BMM150_REG_INT_CONFIG = 0x4e,
69 
70  BMM150_REG_LOW_THRES = 0x4f,
71  BMM150_REG_HIGH_THRES = 0x50,
72 
73  BMM150_REG_REP_XY = 0x51,
74  BMM150_REG_REP_Z = 0x52,
75 
76  // 0x53-0x71 reserved (mostly)
77 
78  // TRIM registers from Bosch BMM050 driver
79  BMM150_REG_TRIM_DIG_X1 = 0x5d,
80  BMM150_REG_TRIM_DIG_Y1 = 0x5e,
81 
82  BMM150_REG_TRIM_DIG_Z4_LSB = 0x62,
83  BMM150_REG_TRIM_DIG_Z4_MSB = 0x63,
84  BMM150_REG_TRIM_DIG_X2 = 0x64,
85  BMM150_REG_TRIM_DIG_Y2 = 0x65,
86 
87  BMM150_REG_TRIM_DIG_Z2_LSB = 0x68,
88  BMM150_REG_TRIM_DIG_Z2_MSB = 0x69,
89  BMM150_REG_TRIM_DIG_Z1_LSB = 0x6a,
90  BMM150_REG_TRIM_DIG_Z1_MSB = 0x6b,
91  BMM150_REG_TRIM_DIG_XYZ1_LSB = 0x6c,
92  BMM150_REG_TRIM_DIG_XYZ1_MSB = 0x6d,
93  BMM150_REG_TRIM_DIG_Z3_LSB = 0x6e,
94  BMM150_REG_TRIM_DIG_Z3_MSB = 0x6f,
95  BMM150_REG_TRIM_DIG_XY2 = 0x70,
96  BMM150_REG_TRIM_DIG_XY1 = 0x71
97  } BMM150_REGS_T;
98 
102  typedef enum {
103  _BMM150_MAG_XY_LSB_RESERVED_BITS = 0x02 | 0x04,
104 
105  BMM150_MAG_XY_LSB_SELFTEST_XY = 0x01,
106 
107  BMM150_MAG_XY_LSB_LSB0 = 0x08,
108  BMM150_MAG_XY_LSB_LSB1 = 0x10,
109  BMM150_MAG_XY_LSB_LSB2 = 0x20,
110  BMM150_MAG_XY_LSB_LSB3 = 0x40,
111  BMM150_MAG_XY_LSB_LSB4 = 0x80,
112  _BMM150_MAG_XY_LSB_LSB_MASK = 31,
113  _BMM150_MAG_XY_LSB_LSB_SHIFT = 3
114  } BMM150_MAG_XY_LSB_BITS_T;
115 
119  typedef enum {
120  BMM150_MAG_Z_LSB_SELFTEST_Z = 0x01,
121 
122  BMM150_MAG_Z_LSB_LSB0 = 0x02,
123  BMM150_MAG_Z_LSB_LSB1 = 0x04,
124  BMM150_MAG_Z_LSB_LSB2 = 0x08,
125  BMM150_MAG_Z_LSB_LSB3 = 0x10,
126  BMM150_MAG_Z_LSB_LSB4 = 0x20,
127  BMM150_MAG_Z_LSB_LSB5 = 0x40,
128  BMM150_MAG_Z_LSB_LSB6 = 0x80,
129  _BMM150_MAG_Z_LSB_LSB_MASK = 127,
130  _BMM150_MAG_Z_LSB_LSB_SHIFT = 1
131  } MAG_Z_LSB_BITS_T;
132 
136  typedef enum {
137  _BMM150_MAG_RHALL_LSB_RESERVED_BITS = 0x02,
138 
139  BMM150_MAG_RHALL_LSB_DATA_READY_STATUS = 0x01,
140 
141  BMM150_MAG_RHALL_LSB_LSB0 = 0x04,
142  BMM150_MAG_RHALL_LSB_LSB1 = 0x08,
143  BMM150_MAG_RHALL_LSB_LSB2 = 0x10,
144  BMM150_MAG_RHALL_LSB_LSB3 = 0x20,
145  BMM150_MAG_RHALL_LSB_LSB4 = 0x40,
146  BMM150_MAG_RHALL_LSB_LSB5 = 0x80,
147  _BMM150_MAG_RHALL_LSB_LSB_MASK = 63,
148  _BMM150_MAG_RHALL_LSB_LSB_SHIFT = 2
149  } BMM150_MAG_RHALL_LSB_BITS_T;
150 
154  typedef enum {
155  BMM150_INT_STATUS_LOW_INT_X = 0x01,
156  BMM150_INT_STATUS_LOW_INT_Y = 0x02,
157  BMM150_INT_STATUS_LOW_INT_Z = 0x04,
158  BMM150_INT_STATUS_HIGH_INT_X = 0x08,
159  BMM150_INT_STATUS_HIGH_INT_Y = 0x10,
160  BMM150_INT_STATUS_HIGH_INT_Z = 0x20,
161  BMM150_INT_STATUS_OVERFLOW = 0x40,
162  BMM150_INT_STATUS_DATA_OVERRUN = 0x80
163  } BMM150_INT_STATUS_BITS_T;
164 
168  typedef enum {
169  _BMM150_POWER_CTRL_RESERVED_BITS = 0x40 | 0x20 | 0x10 | 0x08,
170 
171  BMM150_POWER_CTRL_POWER_CTRL_BIT = 0x01,
172  BMM150_POWER_CTRL_SOFT_RESET0 = 0x02,
173  BMM150_POWER_CTRL_SPI3EN = 0x04, // not supported
174 
175  BMM150_POWER_CTRL_SOFT_RESET1 = 0x80
176  } POWER_CTRL_BITS_T;
177 
181  typedef enum {
182  BMM150_OPMODE_SELFTTEST = 0x01,
183 
184  BMM150_OPMODE_OPERATION_MODE0 = 0x02,
185  BMM150_OPMODE_OPERATION_MODE1 = 0x04,
186  _BMM150_OPMODE_OPERATION_MODE_MASK = 3,
187  _BMM150_OPMODE_OPERATION_MODE_SHIFT = 1,
188 
189  BMM150_OPMODE_DATA_RATE0 = 0x08,
190  BMM150_OPMODE_DATA_RATE1 = 0x10,
191  BMM150_OPMODE_DATA_RATE2 = 0x20,
192  _BMM150_OPMODE_DATA_RATE_MASK = 7,
193  _BMM150_OPMODE_DATA_RATE_SHIFT = 3,
194 
195  BMM150_OPMODE_ADV_SELFTEST0 = 0x40,
196  BMM150_OPMODE_ADV_SELFTEST1 = 0x80,
197  _BMM150_OPMODE_ADV_SELFTEST_MASK = 3,
198  _BMM150_OPMODE_ADV_SELFTEST_SHIFT = 6
199  } OPMODE_BITS_T;
200 
204  typedef enum {
205  BMM150_OPERATION_MODE_NORMAL = 0,
206  BMM150_OPERATION_MODE_FORCED = 1,
207  BMM150_OPERATION_MODE_SLEEP = 3
208  } BMM150_OPERATION_MODE_T;
209 
213  typedef enum {
214  BMM150_DATA_RATE_10HZ = 0,
215  BMM150_DATA_RATE_2HZ = 1,
216  BMM150_DATA_RATE_6HZ = 2,
217  BMM150_DATA_RATE_8HZ = 3,
218  BMM150_DATA_RATE_15HZ = 4,
219  BMM150_DATA_RATE_20HZ = 5,
220  BMM150_DATA_RATE_25HZ = 6,
221  BMM150_DATA_RATE_30HZ = 7
222  } BMM150_DATA_RATE_T;
223 
227  typedef enum {
228  BMM150_INT_EN_LOW_INT_X_EN = 0x01,
229  BMM150_INT_EN_LOW_INT_Y_EN = 0x02,
230  BMM150_INT_EN_LOW_INT_Z_EN = 0x04,
231  BMM150_INT_EN_HIGH_INT_X_EN = 0x08,
232  BMM150_INT_EN_HIGH_INT_Y_EN = 0x10,
233  BMM150_INT_EN_HIGH_INT_Z_EN = 0x20,
234  BMM150_INT_EN_OVERFLOW_INT_EN = 0x40,
235  BMM150_INT_EN_DATA_OVERRUN_INT_EN = 0x80
236  } BMM150_INT_EN_T;
237 
241  typedef enum {
242  BMM150_INT_CONFIG_INT_POLARITY = 0x01,
243  BMM150_INT_CONFIG_INT_LATCH = 0x02,
244  BMM150_INT_CONFIG_DR_POLARITY = 0x04,
245  BMM150_INT_CONFIG_CHANNEL_X = 0x08,
246  BMM150_INT_CONFIG_CHANNEL_Y = 0x10,
247  BMM150_INT_CONFIG_CHANNEL_Z = 0x20,
248  BMM150_INT_CONFIG_INT_PIN_EN = 0x40,
249  BMM150_INT_CONFIG_DR_PIN_EN = 0x80
250  } BMM150_INT_CONFIG_T;
251 
255  typedef enum {
256  BMM150_INTERRUPT_INT,
257  BMM150_INTERRUPT_DR
258  } BMM150_INTERRUPT_PINS_T;
259 
263  typedef enum {
264  BMM150_USAGE_LOW_POWER,
265  BMM150_USAGE_REGULAR,
266  BMM150_USAGE_ENHANCED_REGULAR,
267  BMM150_USAGE_HIGH_ACCURACY
268  } BMM150_USAGE_PRESETS_T;
269 
270 #ifdef __cplusplus
271 }
272 #endif
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