upm  1.7.1
Sensor/Actuator repository for libmraa (v2.0.0)
bno055_regs.h
1 /*
2  * Author: Jon Trulson <jtrulson@ics.com>
3  * Copyright (c) 2016-2017 Intel Corporation.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
20  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 #pragma once
25 
26 #define BNO055_DEFAULT_I2C_BUS 0
27 #define BNO055_DEFAULT_ADDR 0x28
28 
29 // The chip ID, for verification in bno055_init().
30 #define BNO055_CHIPID 0xa0
31 
32 // number of bytes of stored calibration data
33 #define BNO055_CALIBRATION_DATA_SIZE (22)
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
39  // NOTE: Reserved registers should not be written into. Reading
40  // from them will return indeterminate values.
41  //
42  // The register map is divided into two pages - page 1 contains
43  // sensor specific configuration registers, and page 0 contains all
44  // other configuration data and sensor output registers.
45 
49  typedef enum {
50  // The first register listed here is the page ID register. It
51  // is the same on both pages, and selects or indicates the
52  // currently active register page.
53 
54  BNO055_REG_PAGE_ID = 0x07,
55 
56  // Page 0
57  BNO055_REG_CHIP_ID = 0x00,
58  BNO055_REG_ACC_ID = 0x01, // accel id
59  BNO055_REG_MAG_ID = 0x02, // mag id
60  BNO055_REG_GYR_ID = 0x03, // gyro id
61  BNO055_REG_SW_REV_ID_LSB = 0x04,
62  BNO055_REG_SW_REV_ID_MSB = 0x05,
63  BNO055_REG_BL_REV_ID = 0x06, // bootloader rev
64 
65  BNO055_REG_ACC_DATA_X_LSB = 0x08,
66  BNO055_REG_ACC_DATA_X_MSB = 0x09,
67  BNO055_REG_ACC_DATA_Y_LSB = 0x0a,
68  BNO055_REG_ACC_DATA_Y_MSB = 0x0b,
69  BNO055_REG_ACC_DATA_Z_LSB = 0x0c,
70  BNO055_REG_ACC_DATA_Z_MSB = 0x0d,
71 
72  BNO055_REG_MAG_DATA_X_LSB = 0x0e,
73  BNO055_REG_MAG_DATA_X_MSB = 0x0f,
74  BNO055_REG_MAG_DATA_Y_LSB = 0x10,
75  BNO055_REG_MAG_DATA_Y_MSB = 0x11,
76  BNO055_REG_MAG_DATA_Z_LSB = 0x12,
77  BNO055_REG_MAG_DATA_Z_MSB = 0x13,
78 
79  BNO055_REG_GYR_DATA_X_LSB = 0x14,
80  BNO055_REG_GYR_DATA_X_MSB = 0x15,
81  BNO055_REG_GYR_DATA_Y_LSB = 0x16,
82  BNO055_REG_GYR_DATA_Y_MSB = 0x17,
83  BNO055_REG_GYR_DATA_Z_LSB = 0x18,
84  BNO055_REG_GYR_DATA_Z_MSB = 0x19,
85 
86  // euler angles
87  BNO055_REG_EUL_HEADING_LSB = 0x1a,
88  BNO055_REG_EUL_HEADING_MSB = 0x1b,
89  BNO055_REG_EUL_ROLL_LSB = 0x1c,
90  BNO055_REG_EUL_ROLL_MSB = 0x1d,
91  BNO055_REG_EUL_PITCH_LSB = 0x1e,
92  BNO055_REG_EUL_PITCH_MSB = 0x1f,
93 
94  // Quaternions
95  BNO055_REG_QUA_DATA_W_LSB = 0x20,
96  BNO055_REG_QUA_DATA_W_MSB = 0x21,
97  BNO055_REG_QUA_DATA_X_LSB = 0x22,
98  BNO055_REG_QUA_DATA_X_MSB = 0x23,
99  BNO055_REG_QUA_DATA_Y_LSB = 0x24,
100  BNO055_REG_QUA_DATA_Y_MSB = 0x25,
101  BNO055_REG_QUA_DATA_Z_LSB = 0x26,
102  BNO055_REG_QUA_DATA_Z_MSB = 0x27,
103 
104  // linear accel data
105  BNO055_REG_LIA_DATA_X_LSB = 0x28,
106  BNO055_REG_LIA_DATA_X_MSB = 0x29,
107  BNO055_REG_LIA_DATA_Y_LSB = 0x2a,
108  BNO055_REG_LIA_DATA_Y_MSB = 0x2b,
109  BNO055_REG_LIA_DATA_Z_LSB = 0x2c,
110  BNO055_REG_LIA_DATA_Z_MSB = 0x2d,
111 
112  // gravity vector
113  BNO055_REG_GRV_DATA_X_LSB = 0x2e,
114  BNO055_REG_GRV_DATA_X_MSB = 0x2f,
115  BNO055_REG_GRV_DATA_Y_LSB = 0x30,
116  BNO055_REG_GRV_DATA_Y_MSB = 0x31,
117  BNO055_REG_GRV_DATA_Z_LSB = 0x32,
118  BNO055_REG_GRV_DATA_Z_MSB = 0x33,
119 
120  BNO055_REG_TEMPERATURE = 0x34,
121 
122  BNO055_REG_CALIB_STAT = 0x35, // calibration status
123  BNO055_REG_ST_RESULT = 0x36, // selftest result
124 
125  BNO055_REG_INT_STA = 0x37, // interrupt status
126 
127  BNO055_REG_SYS_CLK_STATUS = 0x38,
128 
129  BNO055_REG_SYS_STATUS = 0x39,
130  BNO055_REG_SYS_ERROR = 0x3a,
131 
132  BNO055_REG_UNIT_SEL = 0x3b,
133 
134  // 0x3c reserved
135 
136  BNO055_REG_OPER_MODE = 0x3d, // operating mode
137  BNO055_REG_POWER_MODE = 0x3e,
138 
139  BNO055_REG_SYS_TRIGGER = 0x3f,
140  BNO055_REG_TEMP_SOURCE = 0x40, // temperature src
141 
142  BNO055_REG_AXIS_MAP_CONFIG = 0x41,
143  BNO055_REG_AXIS_MAP_SIGN = 0x42,
144 
145  // 0x43-0x54 reserved
146 
147  // stored calibration data
148  BNO055_REG_ACC_OFFSET_X_LSB = 0x55,
149  BNO055_REG_ACC_OFFSET_X_MSB = 0x56,
150  BNO055_REG_ACC_OFFSET_Y_LSB = 0x57,
151  BNO055_REG_ACC_OFFSET_Y_MSB = 0x58,
152  BNO055_REG_ACC_OFFSET_Z_LSB = 0x59,
153  BNO055_REG_ACC_OFFSET_Z_MSB = 0x5a,
154 
155  BNO055_REG_MAG_OFFSET_X_LSB = 0x5b,
156  BNO055_REG_MAG_OFFSET_X_MSB = 0x5c,
157  BNO055_REG_MAG_OFFSET_Y_LSB = 0x5d,
158  BNO055_REG_MAG_OFFSET_Y_MSB = 0x5e,
159  BNO055_REG_MAG_OFFSET_Z_LSB = 0x5f,
160  BNO055_REG_MAG_OFFSET_Z_MSB = 0x60,
161 
162  BNO055_REG_GYR_OFFSET_X_LSB = 0x61,
163  BNO055_REG_GYR_OFFSET_X_MSB = 0x62,
164  BNO055_REG_GYR_OFFSET_Y_LSB = 0x63,
165  BNO055_REG_GYR_OFFSET_Y_MSB = 0x64,
166  BNO055_REG_GYR_OFFSET_Z_LSB = 0x65,
167  BNO055_REG_GYR_OFFSET_Z_MSB = 0x66,
168 
169  BNO055_REG_ACC_RADIUS_LSB = 0x67,
170  BNO055_REG_ACC_RADIUS_MSB = 0x68,
171 
172  BNO055_REG_MAG_RADIUS_LSB = 0x69,
173  BNO055_REG_MAG_RADIUS_MSB = 0x6a,
174 
175  // 0x6b-0x7f reserved
176  // end of page 0
177 
178  // Page 1
179 
180  // 0x00-0x06 reserved
181  // 0x07 - page id
182 
183  BNO055_REG_ACC_CONFIG = 0x08,
184  BNO055_REG_MAG_CONFIG = 0x09,
185  BNO055_REG_GYR_CONFIG0 = 0x0a,
186  BNO055_REG_GYR_CONFIG1 = 0x0b,
187  BNO055_REG_ACC_SLEEP_CONFIG = 0x0c,
188  BNO055_REG_GYR_SLEEP_CONFIG = 0x0d,
189 
190  // 0x0e reserved
191  BNO055_REG_INT_MSK = 0x0f,
192  BNO055_REG_INT_EN = 0x10,
193 
194  BNO055_REG_ACC_AM_THRES = 0x11,
195  BNO055_REG_ACC_INT_SETTINGS = 0x12,
196  BNO055_REG_ACC_HG_DURATION = 0x13,
197  BNO055_REG_ACC_HG_THRES = 0x14,
198  BNO055_REG_ACC_NM_THRES = 0x15,
199  BNO055_REG_ACC_NM_SET = 0x16,
200 
201  BNO055_REG_GYR_INT_SETTING = 0x17,
202  BNO055_REG_GYR_HR_X_SET = 0x18,
203  BNO055_REG_GYR_DUR_X = 0x19,
204  BNO055_REG_GYR_HR_Y_SET = 0x1a,
205  BNO055_REG_GYR_DUR_Y = 0x1b,
206  BNO055_REG_GYR_HR_Z_SET = 0x1c,
207  BNO055_REG_GYR_DUR_Z = 0x1d,
208  BNO055_REG_GYR_AM_THRES = 0x1e,
209  BNO055_REG_GYR_AM_SET = 0x1f,
210 
211  // 0x20-0x4f reserved
212 
213  // 16 byte (0x50-0x5f) unique ID
214  BNO055_REG_BNO_UNIQUE_ID = 0x50
215 
216  // 0x60-0x7f reserved
217  } BNO055_REGS_T;
218 
219  // Page 0 register enumerants
220 
224  typedef enum {
225  BNO055_CALIB_STAT_MAG0 = 0x01,
226  BNO055_CALIB_STAT_MAG1 = 0x02,
227  _BNO055_CALIB_STAT_MAG_MASK = 3,
228  _BNO055_CALIB_STAT_MAG_SHIFT = 0,
229 
230  BNO055_CALIB_STAT_ACC0 = 0x04,
231  BNO055_CALIB_STAT_ACC1 = 0x08,
232  _BNO055_CALIB_STAT_ACC_MASK = 3,
233  _BNO055_CALIB_STAT_ACC_SHIFT = 2,
234 
235  BNO055_CALIB_STAT_GYR0 = 0x10,
236  BNO055_CALIB_STAT_GYR1 = 0x20,
237  _BNO055_CALIB_STAT_GYR_MASK = 3,
238  _BNO055_CALIB_STAT_GYR_SHIFT = 4,
239 
240  BNO055_CALIB_STAT_SYS0 = 0x40,
241  BNO055_CALIB_STAT_SYS1 = 0x80,
242  _BNO055_CALIB_STAT_SYS_MASK = 3,
243  _BNO055_CALIB_STAT_SYS_SHIFT = 6
244  } BNO055_CALIB_STAT_BITS_T;
245 
249  typedef enum {
250  BNO055_ST_RESULT_ACC = 0x01,
251  BNO055_ST_RESULT_MAG = 0x02,
252  BNO055_ST_RESULT_GYR = 0x04,
253  BNO055_ST_RESULT_MCU = 0x08
254  // 0x10-0x80 reserved
255  } BNO055_ST_RESULT_BITS_T;
256 
260  typedef enum {
261  // 0x01-0x02 reserved
262  BNO055_INT_STA_GYRO_AM = 0x04, // gyro any-motion
263  BNO055_INT_STA_GYR_HIGH_RATE = 0x08,
264  // 0x010 reserved
265  BNO055_INT_STA_ACC_HIGH_G = 0x20,
266  BNO055_INT_STA_ACC_AM = 0x40, // accel any-motion
267  BNO055_INT_STA_ACC_NM = 0x80 // accel no-motion
268  } BNO055_INT_STA_BITS_T;
269 
273  typedef enum {
274  BNO055_SYS_CLK_STATUS_ST_MAIN_CLK = 0x01
275  // 0x02-0x80 reserved
276  } BNO055_SYS_CLK_STATUS_BITS_T;
277 
281  typedef enum {
282  BNO055_SYS_STATUS_IDLE = 0,
283  BNO055_SYS_STATUS_SYS_ERR = 1,
284  BNO055_SYS_STATUS_INIT_PERIPHERALS = 2,
285  BNO055_SYS_STATUS_SYSTEM_INIT = 3,
286  BNO055_SYS_STATUS_EXECUTING_SELFTEST = 4,
287  BNO055_SYS_STATUS_FUSION_RUNNING = 5,
288  BNO055_SYS_STATUS_NO_FUSION_RUNNING = 6
289  } BNO055_SYS_STATUS_T;
290 
294  typedef enum {
295  BNO055_SYS_ERR_NOERROR = 0,
296  BNO055_SYS_ERR_PERIPH_INIT_ERROR = 1,
297  BNO055_SYS_ERR_SYS_INIT_ERROR = 2,
298  BNO055_SYS_ERR_SELFTEST_FAIL_ERROR = 3,
299  BNO055_SYS_ERR_REG_VAL_OUTOFRANGE_ERROR = 4,
300  BNO055_SYS_ERR_REG_ADDR_OUTOFRANGE_ERROR = 5,
301  BNO055_SYS_ERR_REG_WRITE_ERROR = 6,
302  BNO055_SYS_ERR_LP_MODE_NOT_AVAIL_ERROR = 7,
303  BNO055_SYS_ERR_ACC_PWR_MODE_NOT_AVAIL_ERROR = 8,
304  BNO055_SYS_ERR_FUSION_CONFIG_ERROR = 9,
305  BNO055_SYS_ERR_SENSOR_CONFIG_ERROR = 10
306  } BNO055_SYS_ERR_T;
307 
308 
312  typedef enum {
313  BNO055_UNIT_SEL_ACC_UNIT = 0x01, // 0=m/s^2, 1=mg
314  BNO055_UNIT_SEL_GYR_UNIT = 0x02, // 0=dps, 1=rps
315  BNO055_UNIT_SEL_EUL_UNIT = 0x04, // 0=degrees, 1=radians
316  // 0x08 reserved
317  BNO055_UNIT_SEL_TEMP_UNIT = 0x10, // 0=C, 1=F
318  // 0x20-0x40 reserved
319  BNO055_UNIT_SEL_ORI_ANDROID_WINDOWS = 0x80 // 0=windows
320  // orient,
321  // 1=android
322  } BNO055_UNIT_SEL_BITS_T;
323 
327  typedef enum {
328  BNO055_OPR_MODE_OPERATION_MODE0 = 0x01,
329  BNO055_OPR_MODE_OPERATION_MODE1 = 0x02,
330  BNO055_OPR_MODE_OPERATION_MODE2 = 0x04,
331  BNO055_OPR_MODE_OPERATION_MODE3 = 0x08,
332  _BNO055_OPR_MODE_OPERATION_MODE_MASK = 15,
333  _BNO055_OPR_MODE_OPERATION_MODE_SHIFT = 0
334  // 0x10-0x80 reserved
335  } BNO055_OPR_MODE_BITS_T;
336 
340  typedef enum {
341  BNO055_OPERATION_MODE_CONFIGMODE = 0,
342  BNO055_OPERATION_MODE_ACCONLY = 1,
343  BNO055_OPERATION_MODE_MAGONLY = 2,
344  BNO055_OPERATION_MODE_GYROONLY = 3,
345  BNO055_OPERATION_MODE_ACCMAG = 4,
346  BNO055_OPERATION_MODE_ACCGYRO = 5,
347  BNO055_OPERATION_MODE_MAGGYRO = 6,
348  BNO055_OPERATION_MODE_AMG = 7,
349  // fusion modes
350  BNO055_OPERATION_MODE_IMU = 8,
351  BNO055_OPERATION_MODE_COMPASS = 9,
352  BNO055_OPERATION_MODE_M4G = 10,
353  BNO055_OPERATION_MODE_NDOF_FMC_OFF = 11,
354  BNO055_OPERATION_MODE_NDOF = 12
355  } BNO055_OPERATION_MODES_T;
356 
360  typedef enum {
361  BNO055_PWR_MODE_POWER_MODE0 = 0x01,
362  BNO055_PWR_MODE_POWER_MODE1 = 0x02,
363  _BNO055_PWR_MODE_POWER_MODE_MASK = 3,
364  _BNO055_PWR_MODE_POWER_MODE_SHIFT = 0
365  // 0x04-0x80 reserved
366  } BNO055_PWR_MODE_BITS_T;
367 
371  typedef enum {
372  BNO055_POWER_MODE_NORMAL = 0,
373  BNO055_POWER_MODE_LOW = 1,
374  BNO055_POWER_MODE_SUSPEND = 2
375  } POWER_MODES_T;
376 
380  typedef enum {
381  BNO055_SYS_TRIGGER_SELF_TEST = 0x01,
382  // 0x02-0x10 reserved
383  BNO055_SYS_TRIGGER_RST_SYS = 0x20,
384  BNO055_SYS_TRIGGER_RST_INT = 0x40,
385  BNO055_SYS_TRIGGER_CLK_SEL = 0x80
386  } BNO055_SYS_TRIGGER_BITS_T;
387 
391  typedef enum {
392  BNO055_TEMP_SOURCE_TEMP_SOURCE0 = 0x01,
393  BNO055_TEMP_SOURCE_TEMP_SOURCE1 = 0x02,
394  _BNO055_TEMP_SOURCE_TEMP_SOURCE_MASK = 3,
395  _BNO055_TEMP_SOURCE_TEMP_SOURCE_SHIFT = 0
396  // 0x04-0x80 reserved
397  } BNO055_TEMP_SOURCE_BITS_T;
398 
402  typedef enum {
403  BNO055_TEMP_SOURCE_ACC = 0,
404  BNO055_TEMP_SOURCE_GYR = 1
405  } BNO055_TEMP_SOURCES_T;
406 
410  typedef enum {
411  BNO055_AXIS_MAP_CONFIG_REMAPPED_X_VAL0 = 0x01,
412  BNO055_AXIS_MAP_CONFIG_REMAPPED_X_VAL1 = 0x02,
413  _BNO055_AXIS_MAP_CONFIG_REMAPPED_X_VAL_MASK = 3,
414  _BNO055_AXIS_MAP_CONFIG_REMAPPED_X_VAL_SHIFT = 0,
415 
416  BNO055_AXIS_MAP_CONFIG_REMAPPED_Y_VAL0 = 0x04,
417  BNO055_AXIS_MAP_CONFIG_REMAPPED_Y_VAL1 = 0x08,
418  _BNO055_AXIS_MAP_CONFIG_REMAPPED_Y_VAL_MASK = 3,
419  _BNO055_AXIS_MAP_CONFIG_REMAPPED_Y_VAL_SHIFT = 2,
420 
421  BNO055_AXIS_MAP_CONFIG_REMAPPED_Z_VAL0 = 0x10,
422  BNO055_AXIS_MAP_CONFIG_REMAPPED_Z_VAL1 = 0x20,
423  _BNO055_AXIS_MAP_CONFIG_REMAPPED_Z_VAL_MASK = 3,
424  _BNO055_AXIS_MAP_CONFIG_REMAPPED_Z_VAL_SHIFT = 4
425  // 0x40-0x80 reserved
426  } BNO055_AXIS_MAP_CONFIG_BITS_T;
427 
432  typedef enum {
433  BNO055_REMAPPED_AXIS_X = 0,
434  BNO055_REMAPPED_AXIS_Y = 1,
435  BNO055_REMAPPED_AXIS_Z = 2
436  } BNO055_REMAPPED_AXIS_T;
437 
441  typedef enum {
442  BNO055_AXIS_MAP_SIGN_REMAPPED_Z_SIGN = 0x01,
443  BNO055_AXIS_MAP_SIGN_REMAPPED_Y_SIGN = 0x02,
444  BNO055_AXIS_MAP_SIGN_REMAPPED_X_SIGN = 0x04
445  // 0x08-0x80 reserved
446  } BNO055_AXIS_MAP_SIGN_BITS_T;
447 
448  // Page 1 register enumerants
449 
453  typedef enum {
454  BNO055_ACC_CONFIG_ACC_RANGE0 = 0x01,
455  BNO055_ACC_CONFIG_ACC_RANGE1 = 0x02,
456  _BNO055_ACC_CONFIG_ACC_RANGE_MASK = 3,
457  _BNO055_ACC_CONFIG_ACC_RANGE_SHIFT = 0,
458 
459  BNO055_ACC_CONFIG_ACC_BW0 = 0x04,
460  BNO055_ACC_CONFIG_ACC_BW1 = 0x08,
461  BNO055_ACC_CONFIG_ACC_BW2 = 0x10,
462  _BNO055_ACC_CONFIG_ACC_BW_MASK = 7,
463  _BNO055_ACC_CONFIG_ACC_BW_SHIFT = 2,
464 
465  BNO055_ACC_CONFIG_ACC_PWR_MODE0 = 0x20,
466  BNO055_ACC_CONFIG_ACC_PWR_MODE1 = 0x40,
467  BNO055_ACC_CONFIG_ACC_PWR_MODE2 = 0x80,
468  _BNO055_ACC_CONFIG_ACC_PWR_MODE_MASK = 7,
469  _BNO055_ACC_CONFIG_ACC_PWR_MODE_SHIFT = 5
470  } BNO055_ACC_CONFIG_BITS_T;
471 
475  typedef enum {
476  BNO055_ACC_RANGE_2G = 0,
477  BNO055_ACC_RANGE_4G = 1,
478  BNO055_ACC_RANGE_8G = 2,
479  BNO055_ACC_RANGE_16G = 3
480  } BNO055_ACC_RANGE_T;
481 
485  typedef enum {
486  BNO055_ACC_BW_7_81 = 0, // 7.81 Hz
487  BNO055_ACC_BW_15_53 = 1,
488  BNO055_ACC_BW_31_25 = 2,
489  BNO055_ACC_BW_62_5 = 3,
490  BNO055_ACC_BW_125 = 4, // 125 Hz
491  BNO055_ACC_BW_250 = 5,
492  BNO055_ACC_BW_500 = 6,
493  BNO055_ACC_BW_1000 = 7
494  } BNO055_ACC_BW_T;
495 
499  typedef enum {
500  BNO055_ACC_PWR_MODE_NORMAL = 0,
501  BNO055_ACC_PWR_MODE_SUSPEND = 1,
502  BNO055_ACC_PWR_MODE_LOWPOWER1 = 2,
503  BNO055_ACC_PWR_MODE_STANDBY = 3,
504  BNO055_ACC_PWR_MODE_LOWPOWER2 = 4,
505  BNO055_ACC_PWR_MODE_DEEPSUSPEND = 5
506  } BNO055_ACC_PWR_MODE_T;
507 
511  typedef enum {
512  BNO055_MAG_CONFIG_MAG_ODR0 = 0x01,
513  BNO055_MAG_CONFIG_MAG_ODR1 = 0x02,
514  BNO055_MAG_CONFIG_MAG_ODR2 = 0x04,
515  _BNO055_MAG_CONFIG_MAG_ODR_MASK = 7,
516  _BNO055_MAG_CONFIG_MAG_ODR_SHIFT = 0,
517 
518  BNO055_MAG_CONFIG_MAG_OPR_MODE0 = 0x08,
519  BNO055_MAG_CONFIG_MAG_OPR_MODE1 = 0x10,
520  _BNO055_MAG_CONFIG_MAG_OPR_MODE_MASK = 3,
521  _BNO055_MAG_CONFIG_MAG_OPR_MODE_SHIFT = 3,
522 
523  BNO055_MAG_CONFIG_MAG_POWER_MODE0 = 0x20,
524  BNO055_MAG_CONFIG_MAG_POWER_MODE1 = 0x40,
525  _BNO055_MAG_CONFIG_MAG_POWER_MODE_MASK = 3,
526  _BNO055_MAG_CONFIG_MAG_POWER_MODE_SHIFT = 5
527  // 0x80 reserved
528  } BNO055_MAG_CONFIG_BITS_T;
529 
533  typedef enum {
534  BNO055_MAG_ODR_2 = 0, // 2Hz
535  BNO055_MAG_ODR_6 = 1,
536  BNO055_MAG_ODR_8 = 2,
537  BNO055_MAG_ODR_10 = 3,
538  BNO055_MAG_ODR_15 = 4,
539  BNO055_MAG_ODR_20 = 5,
540  BNO055_MAG_ODR_25 = 6,
541  BNO055_MAG_ODR_30 = 7
542  } BNO055_MAG_ODR_T;
543 
547  typedef enum {
548  BNO055_MAG_OPR_LOW = 0, // low power
549  BNO055_MAG_OPR_REGULAR = 1,
550  BNO055_MAG_OPR_ENHANCED_REGULAR = 2,
551  BNO055_MAG_OPR_HIGH_ACCURACY = 3
552  } BNO055_MAG_OPR_T;
553 
557  typedef enum {
558  BNO055_MAG_POWER_NORMAL = 0,
559  BNO055_MAG_POWER_SLEEP = 1,
560  BNO055_MAG_POWER_SUSPEND = 2,
561  BNO055_MAG_POWER_FORCE_MODE = 3
562  } BNO055_MAG_POWER_T;
563 
567  typedef enum {
568  BNO055_GYR_CONFIG0_GYR_RANGE0 = 0x01,
569  BNO055_GYR_CONFIG0_GYR_RANGE1 = 0x02,
570  BNO055_GYR_CONFIG0_GYR_RANGE2 = 0x04,
571  _BNO055_GYR_CONFIG0_GYR_RANGE_MASK = 7,
572  _BNO055_GYR_CONFIG0_GYR_RANGE_SHIFT = 0,
573 
574  BNO055_GYR_CONFIG0_GYR_BW0 = 0x08,
575  BNO055_GYR_CONFIG0_GYR_BW1 = 0x10,
576  BNO055_GYR_CONFIG0_GYR_BW2 = 0x20,
577  _BNO055_GYR_CONFIG0_GYR_BW_MASK = 7,
578  _BNO055_GYR_CONFIG0_GYR_BW_SHIFT = 3
579  // 0x40-0x80 reserved
580  } BNO055_GYR_CONFIG0_BITS_T;
581 
585  typedef enum {
586  BNO055_GYR_RANGE_2000 = 0, // degrees/sec
587  BNO055_GYR_RANGE_1000 = 1,
588  BNO055_GYR_RANGE_500 = 2,
589  BNO055_GYR_RANGE_250 = 3,
590  BNO055_GYR_RANGE_125 = 4
591  } BNO055_GYR_RANGE_T;
592 
596  typedef enum {
597  BNO055_GYR_BW_523 = 0, // Hz
598  BNO055_GYR_BW_230 = 1,
599  BNO055_GYR_BW_116 = 2,
600  BNO055_GYR_BW_47 = 3,
601  BNO055_GYR_BW_23 = 4,
602  BNO055_GYR_BW_12 = 5,
603  BNO055_GYR_BW_64 = 6,
604  BNO055_GYR_BW_32 = 7
605  } BNO055_GYR_BW_T;
606 
610  typedef enum {
611  BNO055_GYR_CONFIG1_GYR_POWER_MODE0 = 0x01,
612  BNO055_GYR_CONFIG1_GYR_POWER_MODE1 = 0x02,
613  BNO055_GYR_CONFIG1_GYR_POWER_MODE2 = 0x04,
614  _BNO055_GYR_CONFIG1_GYR_POWER_MODE_MASK = 7,
615  _BNO055_GYR_CONFIG1_GYR_POWER_MODE_SHIFT = 0
616  // 0x08-0x80 reserved
617  } BNO055_GYR_CONFIG1_BITS_T;
618 
622  typedef enum {
623  BNO055_GYR_POWER_MODE_NORMAL = 0,
624  BNO055_GYR_POWER_MODE_FAST_POWERUP = 1,
625  BNO055_GYR_POWER_MODE_DEEP_SUSPEND = 2,
626  BNO055_GYR_POWER_MODE_SUSPEND = 3,
627  BNO055_GYR_POWER_MODE_ADVANCED_POWERSAVE= 4
628  } BNO055_GYR_POWER_MODE_T;
629 
633  typedef enum {
634  BNO055_ACC_SLEEP_CONFIG_SLP_MODE = 0x01, // 0=event,
635  // 1=equidistant
636  // sample
637 
638  BNO055_ACC_SLEEP_CONFIG_ACC_SLP_DUR0 = 0x02,
639  BNO055_ACC_SLEEP_CONFIG_ACC_SLP_DUR1 = 0x04,
640  BNO055_ACC_SLEEP_CONFIG_ACC_SLP_DUR2 = 0x08,
641  BNO055_ACC_SLEEP_CONFIG_ACC_SLP_DUR3 = 0x10,
642  _BNO055_ACC_SLEEP_CONFIG_ACC_SLP_DUR_MASK = 15,
643  _BNO055_ACC_SLEEP_CONFIG_ACC_SLP_DUR_SHIFT = 1
644  // 0x20-0x80 reserved
645  } BNO055_ACC_SLEEP_CONFIG_BITS_T;
646 
650  typedef enum {
651  BNO055_ACC_SLP_DUR_0_5 = 0, // 0.5ms
652  // same for 1-5
653 
654  BNO055_ACC_SLP_DUR_1 = 6, // 1ms
655  BNO055_ACC_SLP_DUR_2 = 7,
656  BNO055_ACC_SLP_DUR_4 = 8,
657  BNO055_ACC_SLP_DUR_6 = 9,
658  BNO055_ACC_SLP_DUR_10 = 10,
659  BNO055_ACC_SLP_DUR_25 = 11,
660  BNO055_ACC_SLP_DUR_50 = 12,
661  BNO055_ACC_SLP_DUR_100 = 13,
662  BNO055_ACC_SLP_DUR_500 = 14
663  // 15 = 1ms
664  } BNO055_ACC_SLP_DUR_T;
665 
669  typedef enum {
670  BNO055_GYR_SLEEP_CONFIG_GYR_SLEEP_DUR0 = 0x01,
671  BNO055_GYR_SLEEP_CONFIG_GYR_SLEEP_DUR1 = 0x02,
672  BNO055_GYR_SLEEP_CONFIG_GYR_SLEEP_DUR2 = 0x04,
673  _BNO055_GYR_SLEEP_CONFIG_GYR_SLEEP_DUR_MASK = 7,
674  _BNO055_GYR_SLEEP_CONFIG_GYR_SLEEP_DUR_SHIFT = 0,
675 
676  BNO055_GYR_SLEEP_CONFIG_GYR_AUTO_SLP_DUR0 = 0x08,
677  BNO055_GYR_SLEEP_CONFIG_GYR_AUTO_SLP_DUR1 = 0x10,
678  BNO055_GYR_SLEEP_CONFIG_GYR_AUTO_SLP_DUR2 = 0x20,
679  _BNO055_GYR_SLEEP_CONFIG_GYR_AUTO_SLP_DUR_MASK = 7,
680  _BNO055_GYR_SLEEP_CONFIG_GYR_AUTO_SLP_DUR_SHIFT = 3
681  // 0x40-0x80 reserved
682  } BNO055_GYR_SLEEP_CONFIG_BITS_T;
683 
687  typedef enum {
688  BNO055_GYR_SLEEP_DUR_2 = 0, // 2ms
689  BNO055_GYR_SLEEP_DUR_4 = 1,
690  BNO055_GYR_SLEEP_DUR_5 = 2,
691  BNO055_GYR_SLEEP_DUR_8 = 3,
692  BNO055_GYR_SLEEP_DUR_10 = 4,
693  BNO055_GYR_SLEEP_DUR_15 = 5,
694  BNO055_GYR_SLEEP_DUR_18 = 6,
695  BNO055_GYR_SLEEP_DUR_20 = 7
696  } BNO055_GYR_SLEEP_DUR_T;
697 
701  typedef enum {
702  // 0 = illegal
703  BNO055_GYR_AUTO_SLP_DUR_4 = 1, // ms
704  BNO055_GYR_AUTO_SLP_DUR_5 = 2,
705  BNO055_GYR_AUTO_SLP_DUR_8 = 3,
706  BNO055_GYR_AUTO_SLP_DUR_10 = 4,
707  BNO055_GYR_AUTO_SLP_DUR_15 = 5,
708  BNO055_GYR_AUTO_SLP_DUR_20 = 6,
709  BNO055_GYR_AUTO_SLP_DUR_40 = 7
710  } BNO055_GYR_AUTO_SLP_DUR_T;
711 
715  typedef enum {
716  // 0x00-0x02 reserved
717  BNO055_INT_GYRO_AM = 0x04, // gyro any-motion
718  BNO055_INT_GYRO_HIGH_RATE = 0x08,
719  // 0x10 reserved
720  BNO055_INT_ACC_HIGH_G = 0x20,
721  BNO055_INT_ACC_AM = 0x40, // acc any-motion
722  BNO055_INT_ACC_NM = 0x80, // acc no-motion
723  } BNO055_INT_BITS_T;
724 
728  typedef enum {
729  BNO055_ACC_INT_SETTINGS_AM_DUR0 = 0x01,
730  BNO055_ACC_INT_SETTINGS_AM_DUR1 = 0x02,
731  _BNO055_ACC_INT_SETTINGS_AM_DUR_MASK = 3,
732  _BNO055_ACC_INT_SETTINGS_AM_DUR_SHIFT = 0,
733 
734  BNO055_ACC_INT_SETTINGS_AM_NM_X_AXIS = 0x04,
735  BNO055_ACC_INT_SETTINGS_AM_NM_Y_AXIS = 0x08,
736  BNO055_ACC_INT_SETTINGS_AM_NM_Z_AXIS = 0x10,
737 
738  BNO055_ACC_INT_SETTINGS_HG_X_AXIS = 0x20,
739  BNO055_ACC_INT_SETTINGS_HG_Y_AXIS = 0x40,
740  BNO055_ACC_INT_SETTINGS_HG_Z_AXIS = 0x80
741  } BNO055_ACC_INT_SETTINGS_BITS_T;
742 
746  typedef enum {
747  BNO055_ACC_NM_SET_SM_NM = 0x01, // 0=slowmotion,
748  // 1=nomotion
749 
750  BNO055_ACC_NM_SET_SM_NM_DUR0 = 0x02,
751  BNO055_ACC_NM_SET_SM_NM_DUR1 = 0x04,
752  BNO055_ACC_NM_SET_SM_NM_DUR2 = 0x08,
753  BNO055_ACC_NM_SET_SM_NM_DUR3 = 0x10,
754  BNO055_ACC_NM_SET_SM_NM_DUR4 = 0x20,
755  BNO055_ACC_NM_SET_SM_NM_DUR5 = 0x40,
756  _BNO055_ACC_NM_SET_SM_NM_DUR_MASK = 63,
757  _BNO055_ACC_NM_SET_SM_NM_DUR_SHIFT = 1
758  // 0x80 reserved
759  } BNO055_ACC_NM_SET_BITS_T;
760 
764  typedef enum {
765  BNO055_GYR_INT_SETTING_AM_X_AXIS = 0x01,
766  BNO055_GYR_INT_SETTING_AM_Y_AXIS = 0x02,
767  BNO055_GYR_INT_SETTING_AM_Z_AXIS = 0x04,
768 
769  BNO055_GYR_INT_SETTING_HR_X_AXIS = 0x08,
770  BNO055_GYR_INT_SETTING_HR_Y_AXIS = 0x10,
771  BNO055_GYR_INT_SETTING_HR_Z_AXIS = 0x20,
772 
773  BNO055_GYR_INT_SETTING_AM_FILT = 0x40,
774  BNO055_GYR_INT_SETTING_HR_FILT = 0x80
775  } BNO055_GYR_INT_SETTING_BITS_T;
776 
781  typedef enum {
782  BNO055_GYR_HR_XYZ_SET_HR_THRESH0 = 0x01,
783  BNO055_GYR_HR_XYZ_SET_HR_THRESH1 = 0x02,
784  BNO055_GYR_HR_XYZ_SET_HR_THRESH2 = 0x04,
785  BNO055_GYR_HR_XYZ_SET_HR_THRESH3 = 0x08,
786  BNO055_GYR_HR_XYZ_SET_HR_THRESH4 = 0x10,
787  _BNO055_GYR_HR_XYZ_SET_HR_THRESH_MASK = 31,
788  _BNO055_GYR_HR_XYZ_SET_HR_THRESH_SHIFT = 0,
789 
790  BNO055_GYR_HR_XYZ_SET_HR_THRESH_HYST0 = 0x20,
791  BNO055_GYR_HR_XYZ_SET_HR_THRESH_HYST1 = 0x40,
792  _BNO055_GYR_HR_XYZ_SET_HR_THRESH_HYST_MASK = 3,
793  _BNO055_GYR_HR_XYZ_SET_HR_THRESH_HYST_SHIFT = 5
794  } BNO055_GYR_HR_XYZ_SET_BITS_T;
795 
799  typedef enum {
800  BNO055_GYR_AM_SET_SLOPE_SAMPLES0 = 0x01,
801  BNO055_GYR_AM_SET_SLOPE_SAMPLES1 = 0x02,
802  _BNO055_GYR_AM_SET_SLOPE_SAMPLES_MASK = 3,
803  _BNO055_GYR_AM_SET_SLOPE_SAMPLES_SHIFT = 0,
804 
805  BNO055_GYR_AM_SET_AWAKE_DUR0 = 0x04,
806  BNO055_GYR_AM_SET_AWAKE_DUR1 = 0x08,
807  _BNO055_GYR_AM_SET_AWAKE_DUR_MASK = 3,
808  _BNO055_GYR_AM_SET_AWAKE_DUR_SHIFT = 2
809 
810  // 0x10-0x80 reserved
811  } BNO055_GYR_AM_SET_BITS_T;
812 
816  typedef enum {
817  BNO055_SLOPE_SAMPLES_8 = 0, // 8 samples
818  BNO055_SLOPE_SAMPLES_16 = 1,
819  BNO055_SLOPE_SAMPLES_32 = 2,
820  BNO055_SLOPE_SAMPLES_64 = 3
821  } BNO055_SLOPE_SAMPLES_T;
822 
823 #ifdef __cplusplus
824 }
825 #endif
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