upm  1.7.1
Sensor/Actuator repository for libmraa (v2.0.0)
lis2ds12_defs.h
1 /*
2  * Author: Jon Trulson <jtrulson@ics.com>
3  * Copyright (c) 2017 Intel Corporation.
4  *
5  * The MIT License
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining
8  * a copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sublicense, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be
16  * included in all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
21  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26 #pragma once
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 #define LIS2DS12_DEFAULT_I2C_BUS 0
33 #define LIS2DS12_DEFAULT_SPI_BUS 0
34 #define LIS2DS12_DEFAULT_I2C_ADDR 0x1e
35 
36 
37 #define LIS2DS12_CHIPID 0x43
38 
39  // NOTE: Reserved registers must not be written into or permanent
40  // damage can result. Reading from them may return indeterminate
41  // values. Registers containing reserved bitfields must be
42  // written as 0.
43 
47  typedef enum {
48  // 0x00-0x05 reserved
49 
50  LIS2DS12_REG_SENSORHUB1_REG = 0x06,
51  LIS2DS12_REG_SENSORHUB2_REG = 0x07,
52  LIS2DS12_REG_SENSORHUB3_REG = 0x08,
53  LIS2DS12_REG_SENSORHUB4_REG = 0x09,
54  LIS2DS12_REG_SENSORHUB5_REG = 0x0a,
55  LIS2DS12_REG_SENSORHUB6_REG = 0x0b,
56 
57  LIS2DS12_REG_MODULE_8BIT = 0x0c,
58 
59  // 0x0d-0x0e reserved
60 
61  LIS2DS12_REG_WHO_AM_I = 0x0f,
62 
63  // 0x10-0x1f reserved
64 
65  LIS2DS12_REG_CTRL1 = 0x20,
66  LIS2DS12_REG_CTRL2 = 0x21,
67  LIS2DS12_REG_CTRL3 = 0x22,
68  LIS2DS12_REG_CTRL4 = 0x23,
69  LIS2DS12_REG_CTRL5 = 0x24,
70 
71  LIS2DS12_REG_FIFO_CTRL = 0x25,
72 
73  LIS2DS12_REG_OUT_T = 0x26,
74 
75  LIS2DS12_REG_STATUS = 0x27,
76 
77  LIS2DS12_REG_OUT_X_L = 0x28,
78  LIS2DS12_REG_OUT_X_H = 0x29,
79  LIS2DS12_REG_OUT_Y_L = 0x2a,
80  LIS2DS12_REG_OUT_Y_H = 0x2b,
81  LIS2DS12_REG_OUT_Z_L = 0x2c,
82  LIS2DS12_REG_OUT_Z_H = 0x2d,
83 
84  LIS2DS12_REG_FIFO_THS = 0x2e,
85  LIS2DS12_REG_FIFO_SRC = 0x2f,
86  LIS2DS12_REG_FIFO_SAMPLES = 0x30,
87 
88  LIS2DS12_REG_TAP_6D_THS = 0x31,
89  LIS2DS12_REG_INT_DUR = 0x32,
90 
91  LIS2DS12_REG_WAKE_UP_THS = 0x33,
92  LIS2DS12_REG_WAKE_UP_DUR = 0x34,
93 
94  LIS2DS12_REG_FREE_FALL = 0x35,
95 
96  LIS2DS12_REG_STATUS_DUP = 0x36,
97 
98  LIS2DS12_REG_WAKE_UP_SRC = 0x37,
99 
100  LIS2DS12_REG_TAP_SRC = 0x38,
101  LIS2DS12_REG_6D_SRC = 0x39,
102 
103  LIS2DS12_REG_STEP_COUNTER_MINTHS = 0x3a,
104  LIS2DS12_REG_STEP_COUNTER_L = 0x3b,
105  LIS2DS12_REG_STEP_COUNTER_H = 0x3c,
106 
107  LIS2DS12_REG_FUNC_CK_GATE = 0x3d,
108  LIS2DS12_REG_FUNC_SRC = 0x3e,
109  LIS2DS12_REG_FUNC_CTRL = 0x3f,
110  } LIS2DS12_REGS_T;
111 
115  typedef enum {
116  LIS2DS12_CTRL1_BDU = 0x01,
117  LIS2DS12_CTRL1_HF_ODR = 0x02,
118 
119  LIS2DS12_CTRL1_FS0 = 0x04,
120  LIS2DS12_CTRL1_FS1 = 0x08,
121  _LIS2DS12_CTRL1_FS_MASK = 3,
122  _LIS2DS12_CTRL1_FS_SHIFT = 2,
123 
124  LIS2DS12_CTRL1_ODR0 = 0x10,
125  LIS2DS12_CTRL1_ODR1 = 0x20,
126  LIS2DS12_CTRL1_ODR2 = 0x40,
127  LIS2DS12_CTRL1_ODR3 = 0x80,
128  _LIS2DS12_CTRL1_ODR_MASK = 15,
129  _LIS2DS12_CTRL1_ODR_SHIFT = 4,
130  } LIS2DS12_CTRL1_BITS_T;
131 
135  typedef enum {
136  LIS2DS12_FS_2G = 0,
137  // odd ordering in the DS...
138  LIS2DS12_FS_16G = 1,
139  LIS2DS12_FS_4G = 2,
140  LIS2DS12_FS_8G = 3,
141  } LIS2DS12_FS_T;
142 
146  typedef enum {
147  LIS2DS12_ODR_POWER_DOWN = 0,
148 
149  // high resolution modes (14 bit resolution)
150 
151  LIS2DS12_ODR_12_5HZ = 1,
152  LIS2DS12_ODR_25HZ = 2,
153  LIS2DS12_ODR_50HZ = 3,
154  LIS2DS12_ODR_100HZ = 4,
155 
156  // The following items (5, 6, 7) have a dual meaning depending
157  // on whether the HF_ODR bit is set, but they use the same
158  // overlapping ODR values for the ODR bitfield. Since the
159  // bitfield is only 4 bits wide, we add a "virtual" 5th bit to
160  // indicate the HF versions. This is then screened out in the
161  // code and will set the HF bit according to what is selected
162  // here.
163 
164  // CTRL1_HF_ODR == 0 (14 bit resolution)
165  LIS2DS12_ODR_200HZ = 5,
166  LIS2DS12_ODR_400HZ = 6,
167  LIS2DS12_ODR_800HZ = 7,
168 
169  // CTRL1_HF_ODR == 1 (12bit resolution). Add 'virtual' bit 5
170  // value (16) for these HF modes, which we will detect and
171  // screen out in the driver. This simplifies the ODR API.
172  LIS2DS12_ODR_1600HZ = (16 + 5),
173  LIS2DS12_ODR_3200HZ = (16 + 6),
174  LIS2DS12_ODR_6400HZ = (16 + 7),
175 
176  // low power modes (10 bit resolution)
177  LIS2DS12_ODR_LP_1HZ = 8,
178  LIS2DS12_ODR_LP_12_5HZ = 9,
179  LIS2DS12_ODR_LP_25HZ = 10,
180  LIS2DS12_ODR_LP_50HZ = 11,
181  LIS2DS12_ODR_LP_100HZ = 12,
182  LIS2DS12_ODR_LP_200HZ = 13,
183  LIS2DS12_ODR_LP_400HZ = 14,
184  LIS2DS12_ODR_LP_800HZ = 15,
185  } LIS2DS12_ODR_T;
186 
190  typedef enum {
191  LIS2DS12_CTRL2_SIM = 0x01, // SPI 3 wire enable
192  LIS2DS12_CTRL2_I2C_DISABLE = 0x02,
193  LIS2DS12_CTRL2_IF_ADD_INC = 0x04, // auto-increment
194  LIS2DS12_CTRL2_FDS_SLOPE = 0x08,
195  LIS2DS12_CTRL2_FUNC_CFG_ENABLE = 0x10,
196 
197  // 0x20 reserved
198 
199  LIS2DS12_CTRL2_SOFT_RESET = 0x40,
200  LIS2DS12_CTRL2_BOOT = 0x80,
201  } LIS2DS12_CTRL2_BITS_T;
202 
206  typedef enum {
207  LIS2DS12_CTRL3_PP_OD = 0x01, //push-pull/open-drain
208  LIS2DS12_CTRL3_H_LACTIVE = 0x02,
209  LIS2DS12_CTRL3_LIR = 0x04,
210  LIS2DS12_CTRL3_TAP_Z_EN = 0x08,
211  LIS2DS12_CTRL3_TAP_Y_EN = 0x10,
212  LIS2DS12_CTRL3_TAP_X_EN = 0x20,
213 
214  LIS2DS12_CTRL3_ST0 = 0x40,
215  LIS2DS12_CTRL3_ST1 = 0x80,
216  _LIS2DS12_CTRL3_ST_MASK = 3,
217  _LIS2DS12_CTRL3_ST_SHIFT = 6,
218  } LIS2DS12_CTRL3_BITS_T;
219 
223  typedef enum {
224  LIS2DS12_ST_NORMAL = 0,
225  LIS2DS12_ST_POS_SIGN = 1,
226  LIS2DS12_ST_NEG_SIGN = 2
227  } LIS2DS12_ST_T;
228 
232  typedef enum {
233  LIS2DS12_CTRL4_INT1_DRDY = 0x01,
234  LIS2DS12_CTRL4_INT1_FTH = 0x02,
235  LIS2DS12_CTRL4_INT1_6D = 0x04,
236  LIS2DS12_CTRL4_INT1_TAP = 0x08,
237  LIS2DS12_CTRL4_INT1_FF = 0x10,
238  LIS2DS12_CTRL4_INT1_WU = 0x20,
239  LIS2DS12_CTRL4_INT1_S_TAP = 0x40,
240  LIS2DS12_CTRL4_INT1_MASTER_DRDY = 0x80,
241  } LIS2DS12_CTRL4_BITS_T;
242 
246  typedef enum {
247  LIS2DS12_CTRL5_INT2_DRDY = 0x01,
248  LIS2DS12_CTRL5_INT2_FTH = 0x02,
249  LIS2DS12_CTRL5_INT2_STEP_DET = 0x04,
250  LIS2DS12_CTRL5_INT2_SIG_MOT = 0x08,
251  LIS2DS12_CTRL5_INT2_TILT = 0x10,
252  LIS2DS12_CTRL5_INT2_ON_INT1 = 0x20,
253  LIS2DS12_CTRL5_INT2_BOOT = 0x40,
254  LIS2DS12_CTRL5_INT2_DRDY_PULSED = 0x80,
255  } LIS2DS12_CTRL5_BITS_T;
256 
260  typedef enum {
261  LIS2DS12_FIFO_CTRL_IF_CS_PU_DIS = 0x01,
262 
263  // 0x02-0x04 reserved
264 
265  LIS2DS12_FIFO_CTRL_MODULE_TO_FIFO = 0x08,
266  LIS2DS12_FIFO_CTRL_INT2_STEP_COUNT_OV = 0x10,
267 
268  LIS2DS12_FIFO_CTRL_FMODE0 = 0x20,
269  LIS2DS12_FIFO_CTRL_FMODE1 = 0x40,
270  LIS2DS12_FIFO_CTRL_FMODE2 = 0x80,
271  _LIS2DS12_FIFO_CTRL_FMODE_MASK = 7,
272  _LIS2DS12_FIFO_CTRL_FMODE_SHIFT = 5,
273  } LIS2DS12_FIFO_CTRL_BITS_T;
274 
278  typedef enum {
279  LIS2DS12_FMODE_BYPASS = 0,
280  LIS2DS12_FMODE_FIFO = 1,
281  // 2 reserved
282  LIS2DS12_FMODE_CONT_TO_FIFO = 3,
283  LIS2DS12_FMODE_BYPASS_TO_CONT = 4,
284  // 5 reserved
285  LIS2DS12_FMODE_CONT = 6,
286  // 7 reserved
287  } LIS2DS12_FMODE_T;
288 
292  typedef enum {
293  LIS2DS12_STATUS_DRDY = 0x01,
294  LIS2DS12_STATUS_FF_IA = 0x02,
295  LIS2DS12_STATUS_6D_IA = 0x04,
296  LIS2DS12_STATUS_SINGLE_TAP = 0x08,
297  LIS2DS12_STATUS_DOUBLE_TAP = 0x10,
298  LIS2DS12_STATUS_SLEEP_STATE = 0x20,
299  LIS2DS12_STATUS_WU_IA = 0x40,
300  LIS2DS12_STATUS_FIFO_THS = 0x80,
301  } LIS2DS12_STATUS_BITS_T;
302 
306  typedef enum {
307  // 0x01-0x10 reserved
308  LIS2DS12_FIFO_SRC_DIFF8 = 0x20,
309  LIS2DS12_FIFO_SRC_FIFO_OVR = 0x40,
310  LIS2DS12_FIFO_SRC_FTH = 0x80,
311  } LIS2DS12_FIFO_SRC_BITS_T;
312 
316  typedef enum {
317  LIS2DS12_TAP_6D_THS_TAP_THS0 = 0x01,
318  LIS2DS12_TAP_6D_THS_TAP_THS1 = 0x02,
319  LIS2DS12_TAP_6D_THS_TAP_THS2 = 0x04,
320  LIS2DS12_TAP_6D_THS_TAP_THS3 = 0x08,
321  LIS2DS12_TAP_6D_THS_TAP_THS4 = 0x10,
322  _LIS2DS12_TAP_6D_THS_TAP_THS_MASK = 31,
323  _LIS2DS12_TAP_6D_THS_TAP_THS_SHIFT = 0,
324 
325  LIS2DS12_TAP_6D_THS_6D_THS0 = 0x20,
326  LIS2DS12_TAP_6D_THS_6D_THS1 = 0x40,
327  _LIS2DS12_TAP_6D_THS_6D_THS_MASK = 3,
328  _LIS2DS12_TAP_6D_THS_6D_THS_SHIFT = 5,
329 
330  LIS2DS12_TAP_6D_THS_6D_4D_EN = 0x80,
331 
332  } LIS2DS12_TAP_6D_THS_BITS_T;
333 
337  typedef enum {
338  LIS2DS12_6D_THS_6 = 0, // 80 degrees
339  LIS2DS12_6D_THS_11 = 1, // 70 degrees
340  LIS2DS12_6D_THS_16 = 2, // 60 degrees
341  LIS2DS12_6D_THS_21 = 3, // 50 degrees
342  } LIS2DS12_6D_THS_T;
343 
347  typedef enum {
348  LIS2DS12_INT_DUR_SHOCK0 = 0x01,
349  LIS2DS12_INT_DUR_SHOCK1 = 0x02,
350  _LIS2DS12_INT_DUR_SHOCK_MASK = 3,
351  _LIS2DS12_INT_DUR_SHOCK_SHIFT = 0,
352 
353  LIS2DS12_INT_DUR_QUIET0 = 0x04,
354  LIS2DS12_INT_DUR_QUIET1 = 0x08,
355  _LIS2DS12_INT_DUR_QUIET_MASK = 3,
356  _LIS2DS12_INT_DUR_QUIET_SHIFT = 2,
357 
358  LIS2DS12_INT_DUR_LAT0 = 0x10,
359  LIS2DS12_INT_DUR_LAT1 = 0x20,
360  LIS2DS12_INT_DUR_LAT2 = 0x40,
361  LIS2DS12_INT_DUR_LAT3 = 0x80,
362  _LIS2DS12_INT_DUR_LAT_MASK = 15,
363  _LIS2DS12_INT_DUR_LAT_SHIFT = 4,
364 
365  } LIS2DS12_INT_DUR_BITS_T;
366 
370  typedef enum {
371  LIS2DS12_WAKE_UP_THS_WU_THS0 = 0x01,
372  LIS2DS12_WAKE_UP_THS_WU_THS1 = 0x02,
373  LIS2DS12_WAKE_UP_THS_WU_THS2 = 0x04,
374  LIS2DS12_WAKE_UP_THS_WU_THS3 = 0x08,
375  LIS2DS12_WAKE_UP_THS_WU_THS4 = 0x10,
376  LIS2DS12_WAKE_UP_THS_WU_THS5 = 0x20,
377  _LIS2DS12_WAKE_UP_THS_WU_THS_MASK = 63,
378  _LIS2DS12_WAKE_UP_THS_WU_THS_SHIFT = 0,
379 
380  LIS2DS12_WAKE_UP_THS_SLEEP_ON = 0x40,
381  LIS2DS12_WAKE_UP_THS_SINGLE_DOUBLE_TAP = 0x80,
382  } LIS2DS12_WAKE_UP_THS_BITS_T;
383 
387  typedef enum {
388  LIS2DS12_WAKE_UP_DUR_SLEEP_DUR0 = 0x01,
389  LIS2DS12_WAKE_UP_DUR_SLEEP_DUR1 = 0x02,
390  LIS2DS12_WAKE_UP_DUR_SLEEP_DUR2 = 0x04,
391  LIS2DS12_WAKE_UP_DUR_SLEEP_DUR3 = 0x08,
392  _LIS2DS12_WAKE_UP_DUR_SLEEP_DUR_MASK = 15,
393  _LIS2DS12_WAKE_UP_DUR_SLEEP_DUR_SHIFT = 0,
394 
395  LIS2DS12_WAKE_UP_DUR_INT1_FSS7 = 0x10,
396 
397  LIS2DS12_WAKE_UP_DUR_WU_DUR0 = 0x20,
398  LIS2DS12_WAKE_UP_DUR_WU_DUR1 = 0x40,
399  _LIS2DS12_WAKE_UP_DUR_WU_DUR_MASK = 3,
400  _LIS2DS12_WAKE_UP_DUR_WU_DUR_SHIFT = 5,
401 
402  LIS2DS12_WAKE_UP_DUR_FF_DUR5 = 0x80,
403  } LIS2DS12_WAKE_UP_DUR_BITS_T;
404 
408  typedef enum {
409  LIS2DS12_FREE_FALL_FF_THS0 = 0x01,
410  LIS2DS12_FREE_FALL_FF_THS1 = 0x02,
411  LIS2DS12_FREE_FALL_FF_THS2 = 0x04,
412  _LIS2DS12_FREE_FALL_FF_THS_MASK = 7,
413  _LIS2DS12_FREE_FALL_FF_THS_SHIFT = 0,
414 
415  LIS2DS12_FREE_FALL_FF_DUR0 = 0x08,
416  LIS2DS12_FREE_FALL_FF_DUR1 = 0x10,
417  LIS2DS12_FREE_FALL_FF_DUR2 = 0x20,
418  LIS2DS12_FREE_FALL_FF_DUR3 = 0x40,
419  LIS2DS12_FREE_FALL_FF_DUR4 = 0x80,
420  _LIS2DS12_FREE_FALL_FF_MASK = 31,
421  _LIS2DS12_FREE_FALL_FF_SHIFT = 3,
422  } LIS2DS12_FREE_FALL_BITS_T;
423 
427  typedef enum {
428  LIS2DS12_STATUS_DUP_DRDY = 0x01,
429  LIS2DS12_STATUS_DUP_FF_IA = 0x02,
430  LIS2DS12_STATUS_DUP_6D_IA = 0x04,
431  LIS2DS12_STATUS_DUP_SINGLE_TAP = 0x08,
432  LIS2DS12_STATUS_DUP_DOUBLE_TAP = 0x10,
433  LIS2DS12_STATUS_DUP_SLEEP_STATE = 0x20,
434  LIS2DS12_STATUS_DUP_WU_IA = 0x40,
435  LIS2DS12_STATUS_DUP_OVR = 0x80,
436  } LIS2DS12_STATUS_DUP_BITS_T;
437 
441  typedef enum {
442  LIS2DS12_WAKE_UP_SRC_Z_WU = 0x01,
443  LIS2DS12_WAKE_UP_SRC_Y_WU = 0x02,
444  LIS2DS12_WAKE_UP_SRC_X_WU = 0x04,
445 
446  LIS2DS12_WAKE_UP_SRC_WU_IA = 0x08,
447  LIS2DS12_WAKE_UP_SRC_SLEEP_STATE_IA = 0x10,
448  LIS2DS12_WAKE_UP_SRC_FF_IA = 0x20,
449 
450  // 0x40-0x80 reserved
451  } LIS2DS12_WAKE_UP_SRC_BITS_T;
452 
456  typedef enum {
457  LIS2DS12_TAP_SRC_Z_TAP = 0x01,
458  LIS2DS12_TAP_SRC_Y_TAP = 0x02,
459  LIS2DS12_TAP_SRC_X_TAP = 0x04,
460  LIS2DS12_TAP_SRC_TAP_SIGN = 0x08,
461  LIS2DS12_TAP_SRC_DOUBLE_TAP = 0x10,
462  LIS2DS12_TAP_SRC_SINGLE_TAP = 0x20,
463  LIS2DS12_TAP_SRC_TAP_IA = 0x40,
464 
465  // 0x80 reserved
466  } LIS2DS12_TAP_SRC_BITS_T;
467 
471  typedef enum {
472  LIS2DS12_6D_SRC_XL = 0x01,
473  LIS2DS12_6D_SRC_XH = 0x02,
474  LIS2DS12_6D_SRC_YL = 0x04,
475  LIS2DS12_6D_SRC_YH = 0x08,
476  LIS2DS12_6D_SRC_ZL = 0x10,
477  LIS2DS12_6D_SRC_ZH = 0x20,
478 
479  LIS2DS12_6D_IA = 0x40,
480 
481  // 0x80 reserved
482  } LIS2DS12_6D_SRC_BITS_T;
483 
487  typedef enum {
488  LIS2DS12_STEP_COUNTER_MINTHS_SC_MTHS0 = 0x01,
489  LIS2DS12_STEP_COUNTER_MINTHS_SC_MTHS1 = 0x02,
490  LIS2DS12_STEP_COUNTER_MINTHS_SC_MTHS2 = 0x04,
491  LIS2DS12_STEP_COUNTER_MINTHS_SC_MTHS3 = 0x08,
492  LIS2DS12_STEP_COUNTER_MINTHS_SC_MTHS4 = 0x10,
493  LIS2DS12_STEP_COUNTER_MINTHS_SC_MTHS5 = 0x20,
494  _LIS2DS12_STEP_COUNTER_MINTHS_SC_MTHS5_MASK = 63,
495  _LIS2DS12_STEP_COUNTER_MINTHS_SC_MTHS5_SHIFT = 0,
496 
497  LIS2DS12_STEP_COUNTER_MINTHS_PEDO4G = 0x40,
498  LIS2DS12_STEP_COUNTER_MINTHS_RST_NSTEP = 0x80,
499  } LIS2DS12_STEP_COUNTER_MINTHS_BITS_T;
500 
504  typedef enum {
505  LIS2DS12_FUNC_CK_GATE_CK_GATE_FUNC = 0x01,
506  LIS2DS12_FUNC_CK_GATE_STEP_DETECT = 0x02,
507  LIS2DS12_FUNC_CK_GATE_RST_PEDO = 0x04,
508  LIS2DS12_FUNC_CK_GATE_RST_SIGN_MOT = 0x08,
509  LIS2DS12_FUNC_CK_GATE_SIG_MOT_DETECT = 0x10,
510 
511  LIS2DS12_FUNC_CK_GATE_FS_SRC0 = 0x20,
512  LIS2DS12_FUNC_CK_GATE_FS_SRC1 = 0x40,
513  _LIS2DS12_FUNC_CK_GATE_FS_SRC_MASK = 3,
514  _LIS2DS12_FUNC_CK_GATE_FS_SRC_SHIFT = 5,
515 
516  LIS2DS12_FUNC_CK_GATE_TILT_INT = 0x80,
517  } LIS2DS12_FUNC_CK_GATE_BITS_T;
518 
522  typedef enum {
523  LIS2DS12_FS_SRC_NO_SCALE = 0,
524  LIS2DS12_FS_SRC_2G = 1,
525  LIS2DS12_FS_SRC_4G = 2,
526  } LIS2DS12_FS_SRC_T;
527 
531  typedef enum {
532  LIS2DS12_FUNC_SRC_SENSORHUB_END_OP = 0x01,
533  LIS2DS12_FUNC_SRC_MODULE_READY = 0x02,
534  LIS2DS12_FUNC_SRC_RST_TILT = 0x04,
535 
536  // 0x08-0x80 reserved
537  } LIS2DS12_FUNC_SRC_BITS_T;
538 
542  typedef enum {
543  LIS2DS12_FUNC_CTRL_STEP_CNT_ON = 0x01,
544  LIS2DS12_FUNC_CTRL_SIGN_MOT_ON = 0x02,
545  LIS2DS12_FUNC_CTRL_MASTER_ON = 0x04,
546  LIS2DS12_FUNC_CTRL_TUD_EN = 0x08,
547  LIS2DS12_FUNC_CTRL_TILT_ON = 0x10,
548  LIS2DS12_FUNC_CTRL_MODULE_ON = 0x20,
549 
550  // 0x40-0x80 reserved
551  } LIS2DS12_FUNC_CTRL_BITS_T;
552 
553  // interrupt selection for installISR() and uninstallISR()
554  typedef enum {
555  LIS2DS12_INTERRUPT_INT1,
556  LIS2DS12_INTERRUPT_INT2
557  } LIS2DS12_INTERRUPT_PINS_T;
558 
559 #ifdef __cplusplus
560 }
561 #endif
Generated on Wed Nov 21 2018 10:43:51 for upm by   doxygen 1.8.11