upm  1.7.1
Sensor/Actuator repository for libmraa (v2.0.0)
lsm303d_defs.h
1 /*
2  * Author: Jon Trulson <jtrulson@ics.com>
3  * Copyright (c) 2017 Intel Corporation.
4  *
5  * The MIT License
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining
8  * a copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sublicense, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be
16  * included in all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
21  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26 #pragma once
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 
33 #define LSM303D_DEFAULT_I2C_BUS 0
34 #define LSM303D_DEFAULT_I2C_ADDR 0x1e
35 
36 // from the WHO_AM_I_* register
37 #define LSM303D_CHIPID 0x49
38 
39 
40  // Due to the fact that this chip is currently obsolete, we only
41  // support minimum functionality. This register map is not
42  // complete. While all registers are specified, bitfields and
43  // enumerants are only specified for certain registers of
44  // interest. Feel free to add what you need.
45 
46  // NOTE: Reserved registers must not be written into or permanent
47  // damage to the device can result. Reading from them may return
48  // indeterminate values. Registers containing reserved bitfields
49  // must be written as 0.
50 
54  typedef enum {
55 
56  // 0x00-0x04 reserved
57 
58  LSM303D_REG_TEMP_OUT_L = 0x05,
59  LSM303D_REG_TEMP_OUT_H = 0x06,
60 
61  LSM303D_REG_STATUS_M = 0x07,
62 
63  LSM303D_REG_OUT_X_L_M = 0x08,
64  LSM303D_REG_OUT_X_H_M = 0x09,
65  LSM303D_REG_OUT_Y_L_M = 0x0a,
66  LSM303D_REG_OUT_Y_H_M = 0x0b,
67  LSM303D_REG_OUT_Z_L_M = 0x0c,
68  LSM303D_REG_OUT_Z_H_M = 0x0d,
69 
70  // 0x0e reserved
71 
72  LSM303D_REG_WHO_AM_I = 0x0f,
73 
74  // 0x10-0x11 reserved
75 
76  LSM303D_REG_INT_CTRL_M = 0x12,
77  LSM303D_REG_INT_SRC_M = 0x13,
78  LSM303D_REG_INT_THS_L_M = 0x14,
79  LSM303D_REG_INT_THS_H_M = 0x15,
80 
81  LSM303D_REG_OFFSET_X_L_M = 0x16,
82  LSM303D_REG_OFFSET_X_H_M = 0x17,
83  LSM303D_REG_OFFSET_Y_L_M = 0x18,
84  LSM303D_REG_OFFSET_Y_H_M = 0x19,
85  LSM303D_REG_OFFSET_Z_L_M = 0x1a,
86  LSM303D_REG_OFFSET_Z_H_M = 0x1b,
87 
88  LSM303D_REG_REFERENCE_X = 0x1c,
89  LSM303D_REG_REFERENCE_Y = 0x1d,
90  LSM303D_REG_REFERENCE_Z = 0x1e,
91 
92  LSM303D_REG_CTRL0 = 0x1f,
93  LSM303D_REG_CTRL1 = 0x20,
94  LSM303D_REG_CTRL2 = 0x21,
95  LSM303D_REG_CTRL3 = 0x22,
96  LSM303D_REG_CTRL4 = 0x23,
97  LSM303D_REG_CTRL5 = 0x24,
98  LSM303D_REG_CTRL6 = 0x25,
99  LSM303D_REG_CTRL7 = 0x26,
100 
101  LSM303D_REG_STATUS_A = 0x27,
102 
103  LSM303D_REG_OUT_X_L_A = 0x28,
104  LSM303D_REG_OUT_X_H_A = 0x29,
105  LSM303D_REG_OUT_Y_L_A = 0x2a,
106  LSM303D_REG_OUT_Y_H_A = 0x2b,
107  LSM303D_REG_OUT_Z_L_A = 0x2c,
108  LSM303D_REG_OUT_Z_H_A = 0x2d,
109 
110  LSM303D_REG_FIFO_CTRL = 0x2e,
111  LSM303D_REG_FIFO_SRC = 0x2f,
112 
113  LSM303D_REG_IG_CFG1 = 0x30,
114  LSM303D_REG_IG_SRC1 = 0x31,
115  LSM303D_REG_IG_THS1 = 0x32,
116  LSM303D_REG_IG_DUR1 = 0x33,
117  LSM303D_REG_IG_CFG2 = 0x34,
118  LSM303D_REG_IG_SRC2 = 0x35,
119  LSM303D_REG_IG_THS2 = 0x36,
120  LSM303D_REG_IG_DUR2 = 0x37,
121 
122  LSM303D_REG_CLICK_CFG = 0x38,
123  LSM303D_REG_CLICK_SRC = 0x39,
124  LSM303D_REG_CLICK_THS = 0x3a,
125 
126  LSM303D_REG_TIME_LIMIT = 0x3b,
127  LSM303D_REG_TIME_LATENCY = 0x3c,
128  LSM303D_REG_TIME_WINDOW = 0x3d,
129 
130  LSM303D_REG_ACT_THS = 0x3e,
131  LSM303D_REG_ACT_DUR = 0x3f,
132  } LSM303D_REGS_T;
133 
134  // Accelerometer registers
135 
139  typedef enum {
140  LSM303D_CTRL1_AXEN = 0x01, // axis enables
141  LSM303D_CTRL1_AYEN = 0x02,
142  LSM303D_CTRL1_AZEN = 0x04,
143 
144  LSM303D_CTRL1_BDU = 0x08,
145 
146  LSM303D_CTRL1_AODR0 = 0x10,
147  LSM303D_CTRL1_AODR1 = 0x20,
148  LSM303D_CTRL1_AODR2 = 0x40,
149  LSM303D_CTRL1_AODR3 = 0x80,
150  _LSM303D_CTRL1_AODR_MASK = 15,
151  _LSM303D_CTRL1_AODR_SHIFT = 4,
152  } LSM303D_CTRL1_BITS_T;
153 
157  typedef enum {
158  LSM303D_AODR_POWER_DOWN = 0,
159  LSM303D_AODR_3_125HZ = 1, // 3.125Hz
160  LSM303D_AODR_6_25HZ = 2,
161  LSM303D_AODR_12_5HZ = 3,
162  LSM303D_AODR_25HZ = 4,
163  LSM303D_AODR_50HZ = 5,
164  LSM303D_AODR_100HZ = 6,
165  LSM303D_AODR_200HZ = 7,
166  LSM303D_AODR_400HZ = 8,
167  LSM303D_AODR_800HZ = 9,
168  LSM303D_AODR_1600HZ = 10,
169  } LSM303D_AODR_T;
170 
174  typedef enum {
175  LSM303D_CTRL2_SIM = 0x01,
176  LSM303D_CTRL2_AST = 0x02,
177 
178  // 0x04 reserved
179 
180  LSM303D_CTRL2_AFS0 = 0x08, // full scale
181  LSM303D_CTRL2_AFS1 = 0x10,
182  LSM303D_CTRL2_AFS2 = 0x20,
183  _LSM303D_CTRL2_AFS_MASK = 7,
184  _LSM303D_CTRL2_AFS_SHIFT = 3,
185 
186  LSM303D_CTRL2_ABW0 = 0x40,
187  LSM303D_CTRL2_ABW1 = 0x80,
188  _LSM303D_CTRL2_ABW_MASK = 3,
189  _LSM303D_CTRL2_ABW_SHIFT = 6,
190  } LSM303D_CTRL2_BITS_T;
191 
195  typedef enum {
196  LSM303D_AFS_2G = 0, // 2G
197  LSM303D_AFS_4G = 1,
198  LSM303D_AFS_6G = 2,
199  LSM303D_AFS_8G = 3,
200  LSM303D_AFS_16G = 4,
201  } LSM303D_AFS_T;
202 
206  typedef enum {
207  LSM303D_CTRL5_LIR1 = 0x01,
208  LSM303D_CTRL5_LIR2 = 0x02,
209 
210  LSM303D_CTRL5_MODR0 = 0x04, // mag odr
211  LSM303D_CTRL5_MODR1 = 0x08,
212  LSM303D_CTRL5_MODR2 = 0x10,
213  _LSM303D_CTRL5_MODR_MASK = 7,
214  _LSM303D_CTRL5_MODR_SHIFT = 2,
215 
216  LSM303D_CTRL5_M_RES0 = 0x20, // resolution
217  LSM303D_CTRL5_M_RES1 = 0x40,
218  _LSM303D_CTRL5_MRES_MASK = 3,
219  _LSM303D_CTRL5_MRES_SHIFT = 6,
220 
221  LSM303D_CTRL5_TEMP_EN = 0x80,
222  } LSM303D_CTRL5_BITS_T;
223 
227  typedef enum {
228  LSM303D_MODR_3_125HZ = 0, // 3.125Hz
229  LSM303D_MODR_6_25HZ = 1,
230  LSM303D_MODR_12_5HZ = 2,
231  LSM303D_MODR_25HZ = 3,
232  LSM303D_MODR_50HZ = 4,
233  LSM303D_MODR_100HZ = 5,
234  } LSM303D_MODR_T;
235 
239  typedef enum {
240  LSM303D_M_RES_LOW = 0,
241  LSM303D_M_RES_HIGH = 3,
242  } LSM303D_M_RES_T;
243 
247  typedef enum {
248  // 0x01-0x10 reserved
249 
250  LSM303D_CTRL6_MFS0 = 0x20,
251  LSM303D_CTRL6_MFS1 = 0x40,
252  _LSM303D_CTRL6_MFS_MASK = 3,
253  _LSM303D_CTRL6_MFS_SHIFT = 5,
254 
255  // 0x80 reserved
256  } LSM303D_CTRL6_BITS_T;
257 
261  typedef enum {
262  LSM303D_MFS_2 = 0, // 2 Gauss
263  LSM303D_MFS_4 = 1,
264  LSM303D_MFS_8 = 2,
265  LSM303D_MFS_12 = 3,
266  } LSM303D_MFS_T;
267 
271  typedef enum {
272  LSM303D_CTRL7_MD0 = 0x01,
273  LSM303D_CTRL7_MD1 = 0x02,
274  _LSM303D_CTRL7_MD_MASK = 3,
275  _LSM303D_CTRL7_MD_SHIFT = 0,
276 
277  LSM303D_CTRL7_MLP = 0x04,
278 
279  // 0x08 reserved
280 
281  LSM303D_CTRL7_T_ONLY = 0x10,
282  LSM303D_CTRL7_AFDS = 0x20,
283 
284  LSM303D_CTRL7_AHPM0 = 0x40,
285  LSM303D_CTRL7_AHPM1 = 0x80,
286  _LSM303D_CTRL7_AHPM_MASK = 3,
287  _LSM303D_CTRL7_AHPM_SHIFT = 6,
288  } LSM303D_CTRL7_BITS_T;
289 
293  typedef enum {
294  LSM303D_MD_CONTINUOUS = 0,
295  LSM303D_MD_SINGLE = 1,
296  LSM303D_MD_POWER_DOWN = 3, // 2 is pwr down too
297  } LSM303D_MD_T;
298 
299 #ifdef __cplusplus
300 }
301 #endif
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