upm  1.7.1
Sensor/Actuator repository for libmraa (v2.0.0)
lsm6ds3h_defs.h
1 /*
2  * Author: Jon Trulson <jtrulson@ics.com>
3  * Copyright (c) 2017 Intel Corporation.
4  *
5  * The MIT License
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining
8  * a copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sublicense, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be
16  * included in all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
21  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26 #pragma once
27 
28 #define LSM6DS3H_DEFAULT_I2C_BUS 0
29 #define LSM6DS3H_DEFAULT_SPI_BUS 0
30 #define LSM6DS3H_DEFAULT_I2C_ADDR 0x6a
31 
32 #define LSM6DS3H_CHIPID 0x69
33 
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
38  // NOTE: Reserved registers must not be written into or permanent
39  // damage can result. Reading from them may return indeterminate
40  // values. Registers containing reserved bitfields must be
41  // written as 0.
42 
43  // This register map is not complete -- all registers are
44  // enumerated, however not all register bitmaps are enumerated
45  // here. Feel free to add any you need that are missing.
46 
50  typedef enum {
51  // 0x00 reserved
52 
53  LSM6DS3H_REG_FUNC_CFG_ACCESS = 0x01,
54 
55  // 0x02-0x03 reserved
56 
57  LSM6DS3H_REG_SENSOR_SYNC_TIME_FRAME = 0x04,
58 
59  // 0x05 reserved
60 
61  LSM6DS3H_REG_FIFO_CTRL1 = 0x06,
62  LSM6DS3H_REG_FIFO_CTRL2 = 0x07,
63  LSM6DS3H_REG_FIFO_CTRL3 = 0x08,
64  LSM6DS3H_REG_FIFO_CTRL4 = 0x09,
65  LSM6DS3H_REG_FIFO_CTRL5 = 0x0a,
66 
67  LSM6DS3H_REG_ORIENT_CFG_G = 0x0b,
68 
69  // 0x0c reserved
70 
71  LSM6DS3H_REG_INT1_CTRL = 0x0d,
72  LSM6DS3H_REG_INT2_CTRL = 0x0e,
73 
74  LSM6DS3H_REG_WHO_AM_I = 0x0f,
75 
76  LSM6DS3H_REG_CTRL1_XL = 0x10,
77  LSM6DS3H_REG_CTRL2_G = 0x11,
78  LSM6DS3H_REG_CTRL3_C = 0x12,
79  LSM6DS3H_REG_CTRL4_C = 0x13,
80  LSM6DS3H_REG_CTRL5_C = 0x14,
81  LSM6DS3H_REG_CTRL6_C = 0x15,
82  LSM6DS3H_REG_CTRL7_G = 0x16,
83  LSM6DS3H_REG_CTRL8_XL = 0x17,
84  LSM6DS3H_REG_CTRL9_XL = 0x18,
85  LSM6DS3H_REG_CTRL10_C = 0x19,
86 
87  LSM6DS3H_REG_MASTER_CFG = 0x1a,
88  LSM6DS3H_REG_WAKE_UP_SRC = 0x1b,
89  LSM6DS3H_REG_TAP_SRC = 0x1c,
90  LSM6DS3H_REG_TAP_D6D = 0x1d,
91 
92  // also STATUS_SPIAux
93  LSM6DS3H_REG_STATUS = 0x1e,
94 
95  // 0x1f reserved
96 
97  LSM6DS3H_REG_OUT_TEMP_L = 0x20,
98  LSM6DS3H_REG_OUT_TEMP_H = 0x21,
99 
100  LSM6DS3H_REG_OUTX_L_G = 0x22,
101  LSM6DS3H_REG_OUTX_H_G = 0x23,
102  LSM6DS3H_REG_OUTY_L_G = 0x24,
103  LSM6DS3H_REG_OUTY_H_G = 0x25,
104  LSM6DS3H_REG_OUTZ_L_G = 0x26,
105  LSM6DS3H_REG_OUTZ_H_G = 0x27,
106 
107  LSM6DS3H_REG_OUTX_L_XL = 0x28,
108  LSM6DS3H_REG_OUTX_H_XL = 0x29,
109  LSM6DS3H_REG_OUTY_L_XL = 0x2a,
110  LSM6DS3H_REG_OUTY_H_XL = 0x2b,
111  LSM6DS3H_REG_OUTZ_L_XL = 0x2c,
112  LSM6DS3H_REG_OUTZ_H_XL = 0x2d,
113 
114  LSM6DS3H_REG_SENSORHUB1_REG = 0x2e,
115  LSM6DS3H_REG_SENSORHUB2_REG = 0x2f,
116  LSM6DS3H_REG_SENSORHUB3_REG = 0x30,
117  LSM6DS3H_REG_SENSORHUB4_REG = 0x31,
118  LSM6DS3H_REG_SENSORHUB5_REG = 0x32,
119  LSM6DS3H_REG_SENSORHUB6_REG = 0x33,
120  LSM6DS3H_REG_SENSORHUB7_REG = 0x34,
121  LSM6DS3H_REG_SENSORHUB8_REG = 0x35,
122  LSM6DS3H_REG_SENSORHUB9_REG = 0x36,
123  LSM6DS3H_REG_SENSORHUB10_REG = 0x37,
124  LSM6DS3H_REG_SENSORHUB11_REG = 0x38,
125  LSM6DS3H_REG_SENSORHUB12_REG = 0x39,
126 
127  LSM6DS3H_REG_FIFO_STATUS1 = 0x3a,
128  LSM6DS3H_REG_FIFO_STATUS2 = 0x3b,
129  LSM6DS3H_REG_FIFO_STATUS3 = 0x3c,
130  LSM6DS3H_REG_FIFO_STATUS4 = 0x3d,
131 
132  LSM6DS3H_REG_FIFO_DATA_OUT_L = 0x3e,
133  LSM6DS3H_REG_FIFO_DATA_OUT_H = 0x3f,
134 
135  LSM6DS3H_REG_TIMESTAMP0_REG = 0x40,
136  LSM6DS3H_REG_TIMESTAMP1_REG = 0x41,
137  LSM6DS3H_REG_TIMESTAMP2_REG = 0x42,
138 
139  // 0x43-0x48 reserved
140 
141  LSM6DS3H_REG_STEP_TIMESTAMP_L = 0x49,
142  LSM6DS3H_REG_STEP_TIMESTAMP_H = 0x4a,
143 
144  LSM6DS3H_REG_STEP_COUNTER_L = 0x4b,
145  LSM6DS3H_REG_STEP_COUNTER_H = 0x4c,
146 
147  LSM6DS3H_REG_SENSORHUB13_REG = 0x4d,
148  LSM6DS3H_REG_SENSORHUB14_REG = 0x4e,
149  LSM6DS3H_REG_SENSORHUB15_REG = 0x4f,
150  LSM6DS3H_REG_SENSORHUB16_REG = 0x50,
151  LSM6DS3H_REG_SENSORHUB17_REG = 0x51,
152  LSM6DS3H_REG_SENSORHUB18_REG = 0x52,
153 
154  LSM6DS3H_REG_FUNC_SRC = 0x53,
155 
156  // 0x54-0x57 reserved
157 
158  LSM6DS3H_REG_TAP_CFG = 0x58,
159  LSM6DS3H_REG_TAP_THS_6D = 0x59,
160 
161  // where is int_dur1?
162  LSM6DS3H_REG_INT_DUR2 = 0x5a,
163 
164  LSM6DS3H_REG_WAKE_UP_THS = 0x5b,
165  LSM6DS3H_REG_WAKE_UP_DUR = 0x5c,
166 
167  LSM6DS3H_REG_FREE_FALL = 0x5d,
168 
169  LSM6DS3H_REG_MD1_CFG = 0x5e,
170  LSM6DS3H_REG_MD2_CFG = 0x5f,
171 
172  // 0x60-0x65 reserved
173 
174  LSM6DS3H_REG_OUT_MAG_RAW_X_L = 0x66,
175  LSM6DS3H_REG_OUT_MAG_RAW_X_H = 0x67,
176  LSM6DS3H_REG_OUT_MAG_RAW_Y_L = 0x68,
177  LSM6DS3H_REG_OUT_MAG_RAW_Y_H = 0x69,
178  LSM6DS3H_REG_OUT_MAG_RAW_Z_L = 0x6a,
179  LSM6DS3H_REG_OUT_MAG_RAW_Z_H = 0x6b,
180 
181  // 0x6c-0x6f assume reserved, but not listed in DS
182 
183  LSM6DS3H_REG_CTRL_SPIAUX = 0x70,
184  } LSM6DS3H_REGS_T;
185 
189  typedef enum {
190  // 0x00 - 0x40 reserved
191  LSM6DS3H_FUNC_CFG_EN = 0x80,
192  } LSM6DS3H_FUNC_CFG_ACCESS_BITS_T;
193 
197  typedef enum {
198  // 0x00 - 0x40 reserved
199  LSM6DS3H_ORIENT_CFG_G_ORIENT0 = 0x01,
200  LSM6DS3H_ORIENT_CFG_G_ORIENT1 = 0x02,
201  LSM6DS3H_ORIENT_CFG_G_ORIENT2 = 0x04,
202  _LSM6DS3H_ORIENT_CFG_G_ORIENT_MASK = 7,
203  _LSM6DS3H_ORIENT_CFG_G_ORIENT_SHIFT = 0,
204 
205  LSM6DS3H_ORIENT_CFG_G_SIGNZ = 0x08,
206  LSM6DS3H_ORIENT_CFG_G_SIGNY = 0x10,
207  LSM6DS3H_ORIENT_CFG_G_SIGNX = 0x20,
208 
209  // 0x40-0x80 reserved
210  } LSM6DS3H_ORIENT_CFG_G_BITS_T;
211 
215  typedef enum {
216  LSM6DS3H_ORIENT_CFG_G_XYZ = 0,
217  LSM6DS3H_ORIENT_CFG_G_XZY = 1,
218  LSM6DS3H_ORIENT_CFG_G_YXZ = 2,
219  LSM6DS3H_ORIENT_CFG_G_YZX = 3,
220  LSM6DS3H_ORIENT_CFG_G_ZXY = 4,
221  LSM6DS3H_ORIENT_CFG_G_ZYX = 5,
222  } LSM6DS3H_ORIENT_G_ORIENT_T;
223 
227  typedef enum {
228  LSM6DS3H_INT1_CTRL_DRDY_XL = 0x01,
229  LSM6DS3H_INT1_CTRL_DRDY_G = 0x02,
230  LSM6DS3H_INT1_CTRL_BOOT = 0x04,
231  LSM6DS3H_INT1_CTRL_FTH = 0x08,
232  LSM6DS3H_INT1_CTRL_FIFO_OVR = 0x10,
233  LSM6DS3H_INT1_CTRL_FULL_FLAG = 0x20,
234  LSM6DS3H_INT1_CTRL_SIGN_MOT = 0x40,
235  LSM6DS3H_INT1_CTRL_STEP_DETECTOR = 0x80,
236  } LSM6DS3H_INT1_CTRL_BITS_T;
237 
241  typedef enum {
242  LSM6DS3H_INT2_CTRL_DRDY_XL = 0x01,
243  LSM6DS3H_INT2_CTRL_DRDY_G = 0x02,
244  LSM6DS3H_INT2_CTRL_DRDY_TEMP = 0x04,
245  LSM6DS3H_INT2_CTRL_FTH = 0x08,
246  LSM6DS3H_INT2_CTRL_FIFO_OVR = 0x10,
247  LSM6DS3H_INT2_CTRL_FULL_FLAG = 0x20,
248  LSM6DS3H_INT2_CTRL_COUNT_OV = 0x40,
249  LSM6DS3H_INT2_CTRL_STEP_DELTA = 0x80,
250  } LSM6DS3H_INT2_CTRL_BITS_T;
251 
255  typedef enum {
256  LSM6DS3H_CTRL1_XL_BW0 = 0x01,
257  LSM6DS3H_CTRL1_XL_BW1 = 0x02,
258  _LSM6DS3H_CTRL1_XL_BW_MASK = 3,
259  _LSM6DS3H_CTRL1_XL_BW_SHIFT = 0,
260 
261  LSM6DS3H_CTRL1_XL_FS0 = 0x04,
262  LSM6DS3H_CTRL1_XL_FS1 = 0x08,
263  _LSM6DS3H_CTRL1_XL_FS_MASK = 3,
264  _LSM6DS3H_CTRL1_XL_FS_SHIFT = 2,
265 
266  LSM6DS3H_CTRL1_XL_ODR0 = 0x10,
267  LSM6DS3H_CTRL1_XL_ODR1 = 0x20,
268  LSM6DS3H_CTRL1_XL_ODR2 = 0x40,
269  LSM6DS3H_CTRL1_XL_ODR3 = 0x80,
270  _LSM6DS3H_CTRL1_XL_ODR_MASK = 15,
271  _LSM6DS3H_CTRL1_XL_ODR_SHIFT = 4,
272  } LSM6DS3H_CTRL1_XL_BITS_T;
273 
277  typedef enum {
278  LSM6DS3H_XL_BW_400HZ = 0,
279  LSM6DS3H_XL_BW_200HZ = 1,
280  LSM6DS3H_XL_BW_100HZ = 2,
281  LSM6DS3H_XL_BW_50HZ = 3,
282  } LSM6DS3H_XL_BW_T;
283 
287  typedef enum {
288  LSM6DS3H_XL_FS_2G = 0,
289  LSM6DS3H_XL_FS_16G = 1,
290  LSM6DS3H_XL_FS_4G = 2,
291  LSM6DS3H_XL_FS_8G = 3,
292  } LSM6DS3H_XL_FS_T;
293 
297  typedef enum {
298  LSM6DS3H_XL_ODR_POWER_DOWN = 0,
299  LSM6DS3H_XL_ODR_12_5HZ = 1,
300  LSM6DS3H_XL_ODR_26HZ = 2,
301  LSM6DS3H_XL_ODR_52HZ = 3,
302  LSM6DS3H_XL_ODR_104HZ = 4,
303  LSM6DS3H_XL_ODR_208HZ = 5,
304  LSM6DS3H_XL_ODR_416HZ = 6,
305  LSM6DS3H_XL_ODR_833HZ = 7,
306  LSM6DS3H_XL_ODR_1_66KHZ = 8,
307  LSM6DS3H_XL_ODR_3_33KHZ = 9,
308  LSM6DS3H_XL_ODR_6_66KHZ = 10,
309  } LSM6DS3H_XL_ODR_T;
310 
314  typedef enum {
315  // 0x01 reserved
316 
317  LSM6DS3H_CTRL2_G_FS_125 = 0x02,
318 
319  LSM6DS3H_CTRL2_G_FS0 = 0x04,
320  LSM6DS3H_CTRL2_G_FS1 = 0x08,
321  _LSM6DS3H_CTRL2_G_FS_MASK = 3,
322  _LSM6DS3H_CTRL2_G_FS_SHIFT = 2,
323 
324  LSM6DS3H_CTRL2_G_ODR0 = 0x10,
325  LSM6DS3H_CTRL2_G_ODR1 = 0x20,
326  LSM6DS3H_CTRL2_G_ODR2 = 0x40,
327  LSM6DS3H_CTRL2_G_ODR3 = 0x80,
328  _LSM6DS3H_CTRL2_G_ODR_MASK = 0x15,
329  _LSM6DS3H_CTRL2_G_ODR_SHIFT = 0x4,
330  } LSM6DS3H_CTRL2_G_BITS_T;
331 
335  typedef enum {
336  LSM6DS3H_G_FS_245DPS = 0, // degrees per second
337  LSM6DS3H_G_FS_500DPS = 1,
338  LSM6DS3H_G_FS_1000DPS = 2,
339  LSM6DS3H_G_FS_2000DPS = 3,
340 
341  // 125dps is a special case - it's just a bit you set or clear
342  // to enable 125 or disable it. We add a virtual bit 3 (4)
343  // here as a flag to the driver to enable/disable this
344  // "special" FS setting.
345  LSM6DS3H_G_FS_125DPS = (4 + 0),
346  } LSM6DS3H_G_FS_T;
347 
351  typedef enum {
352  LSM6DS3H_G_ODR_POWER_DOWN = 0,
353  LSM6DS3H_G_ODR_12_5HZ = 1,
354  LSM6DS3H_G_ODR_26HZ = 2,
355  LSM6DS3H_G_ODR_52HZ = 3,
356  LSM6DS3H_G_ODR_104HZ = 4,
357  LSM6DS3H_G_ODR_208HZ = 5,
358  LSM6DS3H_G_ODR_416HZ = 6,
359  LSM6DS3H_G_ODR_833HZ = 7,
360  LSM6DS3H_G_ODR_1_66KHZ = 8,
361  } LSM6DS3H_G_ODR_T;
362 
366  typedef enum {
367  LSM6DS3H_CTRL3_SW_RESET = 0x01,
368  LSM6DS3H_CTRL3_BLE = 0x02,
369  LSM6DS3H_CTRL3_IF_INC = 0x04,
370  LSM6DS3H_CTRL3_SIM = 0x08,
371  LSM6DS3H_CTRL3_PP_OD = 0x10,
372  LSM6DS3H_CTRL3_H_LACTIVE = 0x20,
373  LSM6DS3H_CTRL3_BDU = 0x40,
374  LSM6DS3H_CTRL3_BOOT = 0x80,
375  } LSM6DS3H_CTRL3_BITS_T;
376 
380  typedef enum {
381  LSM6DS3H_CTRL4_STOP_ON_FTH = 0x01,
382  LSM6DS3H_CTRL4_3_3KHZ_ODR = 0x02,
383  LSM6DS3H_CTRL4_I2C_DISABLE = 0x04,
384  LSM6DS3H_CTRL4_DRDY_MASK = 0x08,
385  LSM6DS3H_CTRL4_FIFO_TEMP_EN = 0x10,
386  LSM6DS3H_CTRL4_INT2_ON_INT1 = 0x20,
387  LSM6DS3H_CTRL4_SLEEP_G = 0x40,
388  LSM6DS3H_CTRL4_XL_BW_SCAL_ODR = 0x80,
389  } LSM6DS3H_CTRL4_BITS_T;
390 
394  typedef enum {
395  LSM6DS3H_CTRL5_ST_XL0 = 0x01,
396  LSM6DS3H_CTRL5_ST_XL1 = 0x02,
397  _LSM6DS3H_CTRL5_ST_XL_MASK = 3,
398  _LSM6DS3H_CTRL5_ST_XL_SHIFT = 0,
399 
400  LSM6DS3H_CTRL5_ST_G0 = 0x04,
401  LSM6DS3H_CTRL5_ST_G1 = 0x08,
402  _LSM6DS3H_CTRL5_ST_G_MASK = 3,
403  _LSM6DS3H_CTRL5_ST_G_SHIFT = 2,
404 
405  // 0x10 reserved
406 
407  LSM6DS3H_CTRL5_ROUNDING0 = 0x20,
408  LSM6DS3H_CTRL5_ROUNDING1 = 0x40,
409  LSM6DS3H_CTRL5_ROUNDING2 = 0x80,
410  _LSM6DS3H_CTRL5_ROUNDING_MASK = 7,
411  _LSM6DS3H_CTRL5_ROUNDING_SHIFT = 5,
412  } LSM6DS3H_CTRL5_BITS_T;
413 
417  typedef enum {
418  LSM6DS3H_ST_XL_NORMAL = 0,
419  LSM6DS3H_ST_XL_POSITIVE = 1,
420  LSM6DS3H_ST_XL_NEGATIVE = 2,
421  } LSM6DS3H_ST_XL_T;
422 
426  typedef enum {
427  LSM6DS3H_ST_G_NORMAL = 0,
428  LSM6DS3H_ST_G_POSITIVE = 1,
429  LSM6DS3H_ST_G_NEGATIVE = 3,
430  } LSM6DS3H_ST_G_T;
431 
435  typedef enum {
436  // 0x01-0x08 reserved
437  LSM6DS3H_CTRL6_XL_HM_MODE = 0x10,
438  LSM6DS3H_CTRL6_LVL2_EN = 0x20,
439  LSM6DS3H_CTRL6_LVLEN = 0x40,
440  LSM6DS3H_CTRL6_TRIG_EN = 0x80,
441  } LSM6DS3H_CTRL6_BITS_T;
442 
446  typedef enum {
447  // 0x01-0x02 reserved
448  LSM6DS3H_CTRL7_G_ROUNDING_STATUS = 0x04,
449  LSM6DS3H_CTRL7_G_HP_RST = 0x08,
450 
451  LSM6DS3H_CTRL7_G_HPCF0 = 0x10,
452  LSM6DS3H_CTRL7_G_HPCF1 = 0x20,
453  _LSM6DS3H_CTRL7_G_HPCF_MASK = 3,
454  _LSM6DS3H_CTRL7_G_HPCF_SHIFT = 4,
455 
456  LSM6DS3H_CTRL7_G_HP_EN = 0x40,
457  LSM6DS3H_CTRL7_G_HM_MODE = 0x80,
458  } LSM6DS3H_CTRL7_G_BITS_T;
459 
463  typedef enum {
464  LSM6DS3H_G_HPCF_0_0081HZ = 0, // 0.0081hz
465  LSM6DS3H_G_HPCF_0_0324HZ = 1,
466  LSM6DS3H_G_HPCF_2_07HZ = 2,
467  LSM6DS3H_G_HPCF_16_32HZ = 3,
468  } LSM6DS3H_G_HPCF_T;
469 
473  typedef enum {
474  LSM6DS3H_CTRL8_XL_LOW_PASS_ON_6D = 0x01,
475 
476  // 0x02 reserved
477 
478  LSM6DS3H_CTRL8_XL_HP_SLOPE_EN = 0x04,
479 
480  // 0x08-0x10 reserved
481 
482  LSM6DS3H_CTRL8_XL_HPCF0 = 0x20,
483  LSM6DS3H_CTRL8_XL_HPCF1 = 0x40,
484  _LSM6DS3H_CTRL8_XL_HPCF_MASK = 3,
485  _LSM6DS3H_CTRL8_XL_HPCF_SHIFT = 5,
486 
487  LSM6DS3H_CTRL8_XL_LPF2_EN = 0x80,
488  } LSM6DS3H_CTRL8_XL_BITS_T;
489 
493  typedef enum {
494  // 0x01-0x02 reserved
495 
496  LSM6DS3H_CTRL9_XL_SOFT_EN = 0x04,
497  LSM6DS3H_CTRL9_XL_XEN = 0x08,
498  LSM6DS3H_CTRL9_XL_YEN = 0x10,
499  LSM6DS3H_CTRL9_XL_ZEN = 0x20,
500 
501  // 0x40-0x80 reserved
502  } LSM6DS3H_CTRL9_XL_BITS_T;
503 
507  typedef enum {
508  LSM6DS3H_CTRL10_C_SIGN_MOT_EN = 0x01,
509  LSM6DS3H_CTRL10_C_PEDO_RST_STEP = 0x02,
510  LSM6DS3H_CTRL10_C_FUNC_EN = 0x04,
511  LSM6DS3H_CTRL10_C_XEN = 0x08,
512  LSM6DS3H_CTRL10_C_YEN = 0x10,
513  LSM6DS3H_CTRL10_C_ZEN = 0x20,
514 
515  // 0x40-0x80 reserved
516  } LSM6DS3H_CTRL10_C_BITS_T;
517 
521  typedef enum {
522  LSM6DS3H_MASTER_CONFIG_MASTER_ON = 0x01,
523  LSM6DS3H_MASTER_CONFIG_IRON_EN = 0x02,
524  LSM6DS3H_MASTER_CONFIG_PASS_THROUGH_MODE = 0x04,
525  LSM6DS3H_MASTER_CONFIG_PULL_UP_EN = 0x08,
526  LSM6DS3H_MASTER_CONFIG_START_CONFIG = 0x10,
527 
528  // 0x20 reserved
529 
530  LSM6DS3H_MASTER_CONFIG_DATA_VALID_SEL_FIFO = 0x40,
531  LSM6DS3H_MASTER_CONFIG_DRDY_ON_INT1 = 0x80,
532  } LSM6DS3H_MASTER_CONFIG_BITS_T;
533 
537  typedef enum {
538  LSM6DS3H_WAKE_UP_SRC_Z_WU = 0x01,
539  LSM6DS3H_WAKE_UP_SRC_Y_WU = 0x02,
540  LSM6DS3H_WAKE_UP_SRC_X_WU = 0x04,
541  LSM6DS3H_WAKE_UP_SRC_WU_IA = 0x08,
542  LSM6DS3H_WAKE_UP_SRC_SLEEP_STATE_IA = 0x10,
543  LSM6DS3H_WAKE_UP_SRC_FF_AA = 0x20,
544 
545  // 0x40-0x80 reserved
546  } LSM6DS3H_WAKE_UP_SRC_BITS_T;
547 
551  typedef enum {
552  LSM6DS3H_TAP_SRC_Z_TAP = 0x01,
553  LSM6DS3H_TAP_SRC_Y_TAP = 0x02,
554  LSM6DS3H_TAP_SRC_X_TAP = 0x04,
555  LSM6DS3H_TAP_SRC_TAP_SIGN = 0x08,
556  LSM6DS3H_TAP_SRC_DOUBLE_TAP = 0x10,
557  LSM6DS3H_TAP_SRC_SINGLE_TAP = 0x20,
558  LSM6DS3H_TAP_SRC_TAP_IA = 0x40,
559 
560  // 0x80 reserved
561  } LSM6DS3H_TAP_SRC_BITS_T;
562 
566  typedef enum {
567  LSM6DS3H_D6D_SRC_XL = 0x01,
568  LSM6DS3H_D6D_SRC_XH = 0x02,
569  LSM6DS3H_D6D_SRC_YL = 0x04,
570  LSM6DS3H_D6D_SRC_YH = 0x08,
571  LSM6DS3H_D6D_SRC_ZL = 0x10,
572  LSM6DS3H_D6D_SRC_ZH = 0x20,
573  LSM6DS3H_D6D_SRC_D6D_IA = 0x40,
574 
575  // 0x80 reserved
576  } LSM6DS3H_D6D_SRC_BITS_T;
577 
581  typedef enum {
582  LSM6DS3H_STATUS_XLDA = 0x01, // acc data avail
583  LSM6DS3H_STATUS_GDA = 0x02, // gyr data avail
584  LSM6DS3H_STATUS_TDA = 0x04, // temp data avail
585 
586  // 0x08-0x80 reserved
587  } LSM6DS3H_STATUS_BITS_T;
588 
592  typedef enum {
593  LSM6DS3H_FUNC_SRC_SENSORHUB_END_OP = 0x01,
594  LSM6DS3H_FUNC_SRC_SI_END_OP = 0x02,
595 
596  // 0x04 reserved
597 
598  LSM6DS3H_FUNC_SRC_STEP_OVERFLOW = 0x08,
599  LSM6DS3H_FUNC_SRC_STEP_DETECTED = 0x10,
600  LSM6DS3H_FUNC_SRC_TILT_IA = 0x20,
601  LSM6DS3H_FUNC_SRC_SIGN_MOTION_IA = 0x40,
602  LSM6DS3H_FUNC_SRC_STEP_COUNT_DELTA_IA = 0x80,
603  } LSM6DS3H_FUNC_SRC_BITS_T;
604 
609  typedef enum {
610  LSM6DS3H_MD1_CFG_TIMER = 0x01,
611  LSM6DS3H_MD1_CFG_TILT = 0x02,
612  LSM6DS3H_MD1_CFG_6D = 0x04,
613  LSM6DS3H_MD1_CFG_DOUBLE_TAP = 0x08,
614  LSM6DS3H_MD1_CFG_FF = 0x10,
615  LSM6DS3H_MD1_CFG_WU = 0x20,
616  LSM6DS3H_MD1_CFG_SINGLE_TAP = 0x40,
617  LSM6DS3H_MD1_CFG_INACT_STATE = 0x80,
618  } LSM6DS3H_MD1_CFG_BITS_T;
619 
624  typedef enum {
625  LSM6DS3H_MD2_CFG_IRON = 0x01,
626  LSM6DS3H_MD2_CFG_TILT = 0x02,
627  LSM6DS3H_MD2_CFG_6D = 0x04,
628  LSM6DS3H_MD2_CFG_DOUBLE_TAP = 0x08,
629  LSM6DS3H_MD2_CFG_FF = 0x10,
630  LSM6DS3H_MD2_CFG_WU = 0x20,
631  LSM6DS3H_MD2_CFG_SINGLE_TAP = 0x40,
632  LSM6DS3H_MD2_CFG_INACT_STATE = 0x80,
633  } LSM6DS3H_MD2_CFG_BITS_T;
634 
635  // interrupt selection for installISR() and uninstallISR()
636  typedef enum {
637  LSM6DS3H_INTERRUPT_INT1,
638  LSM6DS3H_INTERRUPT_INT2
639  } LSM6DS3H_INTERRUPT_PINS_T;
640 
641 
642 #ifdef __cplusplus
643 }
644 #endif
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