upm  1.7.1
Sensor/Actuator repository for libmraa (v2.0.0)
lsm6dsl_defs.h
1 /*
2  * Author: Jon Trulson <jtrulson@ics.com>
3  * Copyright (c) 2017 Intel Corporation.
4  *
5  * The MIT License
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining
8  * a copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sublicense, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be
16  * included in all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
21  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26 #pragma once
27 
28 #define LSM6DSL_DEFAULT_I2C_BUS 0
29 #define LSM6DSL_DEFAULT_SPI_BUS 0
30 #define LSM6DSL_DEFAULT_I2C_ADDR 0x6a
31 
32 #define LSM6DSL_CHIPID 0x6a
33 
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
38  // NOTE: Reserved registers must not be written into or permanent
39  // damage can result. Reading from them may return indeterminate
40  // values. Registers containing reserved bitfields must be
41  // written as 0.
42 
43  // This register map is not complete -- all registers are
44  // enumerated, however not all register bitmaps are enumerated
45  // here. Feel free to add any you need that are missing.
46 
50  typedef enum {
51  // 0x00 reserved
52 
53  LSM6DSL_REG_FUNC_CFG_ACCESS = 0x01,
54 
55  // 0x02-0x03 reserved
56 
57  LSM6DSL_REG_SENSOR_SYNC_TIME_FRAME = 0x04,
58 
59  LSM6DSL_REG_SENSOR_SYNC_RES_RATIO = 0x05,
60 
61  LSM6DSL_REG_FIFO_CTRL1 = 0x06,
62  LSM6DSL_REG_FIFO_CTRL2 = 0x07,
63  LSM6DSL_REG_FIFO_CTRL3 = 0x08,
64  LSM6DSL_REG_FIFO_CTRL4 = 0x09,
65  LSM6DSL_REG_FIFO_CTRL5 = 0x0a,
66 
67  LSM6DSL_REG_DRDY_PULSE_CFG_G = 0x0b,
68 
69  // 0x0c reserved
70 
71  LSM6DSL_REG_INT1_CTRL = 0x0d,
72  LSM6DSL_REG_INT2_CTRL = 0x0e,
73 
74  LSM6DSL_REG_WHO_AM_I = 0x0f,
75 
76  LSM6DSL_REG_CTRL1_XL = 0x10,
77  LSM6DSL_REG_CTRL2_G = 0x11,
78  LSM6DSL_REG_CTRL3_C = 0x12,
79  LSM6DSL_REG_CTRL4_C = 0x13,
80  LSM6DSL_REG_CTRL5_C = 0x14,
81  LSM6DSL_REG_CTRL6_C = 0x15,
82  LSM6DSL_REG_CTRL7_G = 0x16,
83  LSM6DSL_REG_CTRL8_XL = 0x17,
84  LSM6DSL_REG_CTRL9_XL = 0x18,
85  LSM6DSL_REG_CTRL10_C = 0x19,
86 
87  LSM6DSL_REG_MASTER_CFG = 0x1a,
88  LSM6DSL_REG_WAKE_UP_SRC = 0x1b,
89  LSM6DSL_REG_TAP_SRC = 0x1c,
90  LSM6DSL_REG_D6D_SRC = 0x1d,
91 
92  LSM6DSL_REG_STATUS = 0x1e,
93 
94  // 0x1f reserved
95 
96  LSM6DSL_REG_OUT_TEMP_L = 0x20,
97  LSM6DSL_REG_OUT_TEMP_H = 0x21,
98 
99  LSM6DSL_REG_OUTX_L_G = 0x22,
100  LSM6DSL_REG_OUTX_H_G = 0x23,
101  LSM6DSL_REG_OUTY_L_G = 0x24,
102  LSM6DSL_REG_OUTY_H_G = 0x25,
103  LSM6DSL_REG_OUTZ_L_G = 0x26,
104  LSM6DSL_REG_OUTZ_H_G = 0x27,
105 
106  LSM6DSL_REG_OUTX_L_XL = 0x28,
107  LSM6DSL_REG_OUTX_H_XL = 0x29,
108  LSM6DSL_REG_OUTY_L_XL = 0x2a,
109  LSM6DSL_REG_OUTY_H_XL = 0x2b,
110  LSM6DSL_REG_OUTZ_L_XL = 0x2c,
111  LSM6DSL_REG_OUTZ_H_XL = 0x2d,
112 
113  LSM6DSL_REG_SENSORHUB1_REG = 0x2e,
114  LSM6DSL_REG_SENSORHUB2_REG = 0x2f,
115  LSM6DSL_REG_SENSORHUB3_REG = 0x30,
116  LSM6DSL_REG_SENSORHUB4_REG = 0x31,
117  LSM6DSL_REG_SENSORHUB5_REG = 0x32,
118  LSM6DSL_REG_SENSORHUB6_REG = 0x33,
119  LSM6DSL_REG_SENSORHUB7_REG = 0x34,
120  LSM6DSL_REG_SENSORHUB8_REG = 0x35,
121  LSM6DSL_REG_SENSORHUB9_REG = 0x36,
122  LSM6DSL_REG_SENSORHUB10_REG = 0x37,
123  LSM6DSL_REG_SENSORHUB11_REG = 0x38,
124  LSM6DSL_REG_SENSORHUB12_REG = 0x39,
125 
126  LSM6DSL_REG_FIFO_STATUS1 = 0x3a,
127  LSM6DSL_REG_FIFO_STATUS2 = 0x3b,
128  LSM6DSL_REG_FIFO_STATUS3 = 0x3c,
129  LSM6DSL_REG_FIFO_STATUS4 = 0x3d,
130 
131  LSM6DSL_REG_FIFO_DATA_OUT_L = 0x3e,
132  LSM6DSL_REG_FIFO_DATA_OUT_H = 0x3f,
133 
134  LSM6DSL_REG_TIMESTAMP0_REG = 0x40,
135  LSM6DSL_REG_TIMESTAMP1_REG = 0x41,
136  LSM6DSL_REG_TIMESTAMP2_REG = 0x42,
137 
138  // 0x43-0x48 reserved
139 
140  LSM6DSL_REG_STEP_TIMESTAMP_L = 0x49,
141  LSM6DSL_REG_STEP_TIMESTAMP_H = 0x4a,
142 
143  LSM6DSL_REG_STEP_COUNTER_L = 0x4b,
144  LSM6DSL_REG_STEP_COUNTER_H = 0x4c,
145 
146  LSM6DSL_REG_SENSORHUB13_REG = 0x4d,
147  LSM6DSL_REG_SENSORHUB14_REG = 0x4e,
148  LSM6DSL_REG_SENSORHUB15_REG = 0x4f,
149  LSM6DSL_REG_SENSORHUB16_REG = 0x50,
150  LSM6DSL_REG_SENSORHUB17_REG = 0x51,
151  LSM6DSL_REG_SENSORHUB18_REG = 0x52,
152 
153  LSM6DSL_REG_FUNC_SRC1 = 0x53,
154  LSM6DSL_REG_FUNC_SRC2 = 0x54,
155 
156  LSM6DSL_REG_WRIST_TILT_IA = 0x55,
157 
158  // 0x56-0x57 reserved
159 
160  LSM6DSL_REG_TAP_CFG = 0x58,
161  LSM6DSL_REG_TAP_THS_6D = 0x59,
162 
163  LSM6DSL_REG_INT_DUR2 = 0x5a,
164 
165  LSM6DSL_REG_WAKE_UP_THS = 0x5b,
166  LSM6DSL_REG_WAKE_UP_DUR = 0x5c,
167 
168  LSM6DSL_REG_FREE_FALL = 0x5d,
169 
170  LSM6DSL_REG_MD1_CFG = 0x5e,
171  LSM6DSL_REG_MD2_CFG = 0x5f,
172 
173  LSM6DSL_REG_MASTER_CMD_CODE = 0x60,
174  LSM6DSL_REG_SENS_SYNC_SPI_ERROR_CODE = 0x61,
175 
176  // 0x62-0x65 reserved
177 
178  LSM6DSL_REG_OUT_MAG_RAW_X_L = 0x66,
179  LSM6DSL_REG_OUT_MAG_RAW_X_H = 0x67,
180  LSM6DSL_REG_OUT_MAG_RAW_Y_L = 0x68,
181  LSM6DSL_REG_OUT_MAG_RAW_Y_H = 0x69,
182  LSM6DSL_REG_OUT_MAG_RAW_Z_L = 0x6a,
183  LSM6DSL_REG_OUT_MAG_RAW_Z_H = 0x6b,
184 
185  // 0x6c-0x72 reserved
186 
187  LSM6DSL_REG_X_OFS_USR = 0x73,
188  LSM6DSL_REG_Y_OFS_USR = 0x74,
189  LSM6DSL_REG_Z_OFS_USR = 0x75,
190 
191  // 0x76-0x7f reserved
192  } LSM6DSL_REGS_T;
193 
197  typedef enum {
198  // 0x00-0x10 reserved
199 
200  LSM6DSL_FUNC_CFG_EN_B = 0x20,
201 
202  // 0x4 reserved
203 
204  LSM6DSL_FUNC_CFG_EN = 0x80,
205  } LSM6DSL_FUNC_CFG_ACCESS_BITS_T;
206 
210  typedef enum {
211  LSM6DSL_SENSOR_SYNC_TIME_FRAME0 = 0x01,
212  LSM6DSL_SENSOR_SYNC_TIME_FRAME1 = 0x02,
213  LSM6DSL_SENSOR_SYNC_TIME_FRAME2 = 0x04,
214  LSM6DSL_SENSOR_SYNC_TIME_FRAME3 = 0x08,
215  _LSM6DSL_SENSOR_SYNC_TIME_MASK = 15,
216  _LSM6DSL_SENSOR_SYNC_TIME_SHIFT = 0,
217 
218  // 0x10-0x80 reserved
219  } LSM6DSL_SENSOR_SYNC_TIME_FRAME_BITS_T;
220 
224  typedef enum {
225  LSM6DSL_DRDY_PULSE_CFG_G_INT2_WRIST_TILT = 0x01,
226 
227  // 0x02-0x40 reserved
228 
229  LSM6DSL_DRDY_PULSE_CFG_G_DRDY_PULSED = 0x80,
230  } LSM6DSL_DRDY_PULSE_CFG_G_BITS_T;
231 
235  typedef enum {
236  LSM6DSL_INT1_CTRL_DRDY_XL = 0x01,
237  LSM6DSL_INT1_CTRL_DRDY_G = 0x02,
238  LSM6DSL_INT1_CTRL_BOOT = 0x04,
239  LSM6DSL_INT1_CTRL_FTH = 0x08,
240  LSM6DSL_INT1_CTRL_FIFO_OVR = 0x10,
241  LSM6DSL_INT1_CTRL_FULL_FLAG = 0x20,
242  LSM6DSL_INT1_CTRL_SIGN_MOT = 0x40,
243  LSM6DSL_INT1_CTRL_STEP_DETECTOR = 0x80,
244  } LSM6DSL_INT1_CTRL_BITS_T;
245 
249  typedef enum {
250  LSM6DSL_INT2_CTRL_DRDY_XL = 0x01,
251  LSM6DSL_INT2_CTRL_DRDY_G = 0x02,
252  LSM6DSL_INT2_CTRL_DRDY_TEMP = 0x04,
253  LSM6DSL_INT2_CTRL_FTH = 0x08,
254  LSM6DSL_INT2_CTRL_FIFO_OVR = 0x10,
255  LSM6DSL_INT2_CTRL_FULL_FLAG = 0x20,
256  LSM6DSL_INT2_CTRL_COUNT_OV = 0x40,
257  LSM6DSL_INT2_CTRL_STEP_DELTA = 0x80,
258  } LSM6DSL_INT2_CTRL_BITS_T;
259 
263  typedef enum {
264  LSM6DSL_CTRL1_XL_BW0 = 0x01,
265  LSM6DSL_CTRL1_XL_LPF1_BW_SEL = 0x02,
266 
267  LSM6DSL_CTRL1_XL_FS0 = 0x04,
268  LSM6DSL_CTRL1_XL_FS1 = 0x08,
269  _LSM6DSL_CTRL1_XL_FS_MASK = 3,
270  _LSM6DSL_CTRL1_XL_FS_SHIFT = 2,
271 
272  LSM6DSL_CTRL1_XL_ODR0 = 0x10,
273  LSM6DSL_CTRL1_XL_ODR1 = 0x20,
274  LSM6DSL_CTRL1_XL_ODR2 = 0x40,
275  LSM6DSL_CTRL1_XL_ODR3 = 0x80,
276  _LSM6DSL_CTRL1_XL_ODR_MASK = 15,
277  _LSM6DSL_CTRL1_XL_ODR_SHIFT = 4,
278  } LSM6DSL_CTRL1_XL_BITS_T;
279 
283  typedef enum {
284  LSM6DSL_XL_FS_2G = 0,
285  LSM6DSL_XL_FS_16G = 1,
286  LSM6DSL_XL_FS_4G = 2,
287  LSM6DSL_XL_FS_8G = 3,
288  } LSM6DSL_XL_FS_T;
289 
293  typedef enum {
294  LSM6DSL_XL_ODR_POWER_DOWN = 0,
295  LSM6DSL_XL_ODR_12_5HZ = 1,
296  LSM6DSL_XL_ODR_26HZ = 2,
297  LSM6DSL_XL_ODR_52HZ = 3,
298  LSM6DSL_XL_ODR_104HZ = 4,
299  LSM6DSL_XL_ODR_208HZ = 5,
300  LSM6DSL_XL_ODR_416HZ = 6,
301  LSM6DSL_XL_ODR_833HZ = 7,
302  LSM6DSL_XL_ODR_1_66KHZ = 8,
303  LSM6DSL_XL_ODR_3_33KHZ = 9,
304  LSM6DSL_XL_ODR_6_66KHZ = 10,
305  } LSM6DSL_XL_ODR_T;
306 
310  typedef enum {
311  // 0x01 reserved
312 
313  LSM6DSL_CTRL2_G_FS_125 = 0x02,
314 
315  LSM6DSL_CTRL2_G_FS0 = 0x04,
316  LSM6DSL_CTRL2_G_FS1 = 0x08,
317  _LSM6DSL_CTRL2_G_FS_MASK = 3,
318  _LSM6DSL_CTRL2_G_FS_SHIFT = 2,
319 
320  LSM6DSL_CTRL2_G_ODR0 = 0x10,
321  LSM6DSL_CTRL2_G_ODR1 = 0x20,
322  LSM6DSL_CTRL2_G_ODR2 = 0x40,
323  LSM6DSL_CTRL2_G_ODR3 = 0x80,
324  _LSM6DSL_CTRL2_G_ODR_MASK = 0x15,
325  _LSM6DSL_CTRL2_G_ODR_SHIFT = 0x4,
326  } LSM6DSL_CTRL2_G_BITS_T;
327 
331  typedef enum {
332  LSM6DSL_G_FS_245DPS = 0, // degrees per second
333  LSM6DSL_G_FS_500DPS = 1,
334  LSM6DSL_G_FS_1000DPS = 2,
335  LSM6DSL_G_FS_2000DPS = 3,
336 
337  // 125dps is a special case - it's just a bit you set or clear
338  // to enable 125 or disable it. We add a virtual bit 3 (4)
339  // here as a flag to the driver to enable/disable this
340  // "special" FS setting.
341  LSM6DSL_G_FS_125DPS = (4 + 0),
342  } LSM6DSL_G_FS_T;
343 
347  typedef enum {
348  LSM6DSL_G_ODR_POWER_DOWN = 0,
349  LSM6DSL_G_ODR_12_5HZ = 1,
350  LSM6DSL_G_ODR_26HZ = 2,
351  LSM6DSL_G_ODR_52HZ = 3,
352  LSM6DSL_G_ODR_104HZ = 4,
353  LSM6DSL_G_ODR_208HZ = 5,
354  LSM6DSL_G_ODR_416HZ = 6,
355  LSM6DSL_G_ODR_833HZ = 7,
356  LSM6DSL_G_ODR_1_66KHZ = 8,
357  LSM6DSL_G_ODR_3_33KHZ = 9,
358  LSM6DSL_G_ODR_6_66KHZ = 10,
359  } LSM6DSL_G_ODR_T;
360 
364  typedef enum {
365  LSM6DSL_CTRL3_SW_RESET = 0x01,
366  LSM6DSL_CTRL3_BLE = 0x02,
367  LSM6DSL_CTRL3_IF_INC = 0x04,
368  LSM6DSL_CTRL3_SIM = 0x08,
369  LSM6DSL_CTRL3_PP_OD = 0x10,
370  LSM6DSL_CTRL3_H_LACTIVE = 0x20,
371  LSM6DSL_CTRL3_BDU = 0x40,
372  LSM6DSL_CTRL3_BOOT = 0x80,
373  } LSM6DSL_CTRL3_BITS_T;
374 
378  typedef enum {
379  // 0x01 reserved
380 
381  LSM6DSL_CTRL4_LPF1_SEL_G = 0x02,
382  LSM6DSL_CTRL4_I2C_DISABLE = 0x04,
383  LSM6DSL_CTRL4_DRDY_MASK = 0x08,
384  LSM6DSL_CTRL4_DEN_SRSY_INT1 = 0x10,
385  LSM6DSL_CTRL4_INT2_ON_INT1 = 0x20,
386  LSM6DSL_CTRL4_SLEEP = 0x40,
387  LSM6DSL_CTRL4_DEN_XL_EN = 0x80,
388  } LSM6DSL_CTRL4_BITS_T;
389 
393  typedef enum {
394  LSM6DSL_CTRL5_ST_XL0 = 0x01,
395  LSM6DSL_CTRL5_ST_XL1 = 0x02,
396  _LSM6DSL_CTRL5_ST_XL_MASK = 3,
397  _LSM6DSL_CTRL5_ST_XL_SHIFT = 0,
398 
399  LSM6DSL_CTRL5_ST_G0 = 0x04,
400  LSM6DSL_CTRL5_ST_G1 = 0x08,
401  _LSM6DSL_CTRL5_ST_G_MASK = 3,
402  _LSM6DSL_CTRL5_ST_G_SHIFT = 2,
403 
404  LSM6DSL_CTRL5_DEN_LH = 0x10,
405 
406  LSM6DSL_CTRL5_ROUNDING0 = 0x20,
407  LSM6DSL_CTRL5_ROUNDING1 = 0x40,
408  LSM6DSL_CTRL5_ROUNDING2 = 0x80,
409  _LSM6DSL_CTRL5_ROUNDING_MASK = 7,
410  _LSM6DSL_CTRL5_ROUNDING_SHIFT = 5,
411  } LSM6DSL_CTRL5_BITS_T;
412 
416  typedef enum {
417  LSM6DSL_ST_XL_NORMAL = 0,
418  LSM6DSL_ST_XL_POSITIVE = 1,
419  LSM6DSL_ST_XL_NEGATIVE = 2,
420  } LSM6DSL_ST_XL_T;
421 
425  typedef enum {
426  LSM6DSL_ST_G_NORMAL = 0,
427  LSM6DSL_ST_G_POSITIVE = 1,
428  LSM6DSL_ST_G_NEGATIVE = 3,
429  } LSM6DSL_ST_G_T;
430 
434  typedef enum {
435  LSM6DSL_CTRL6_FTYPE0 = 0x01, // gyr lp filter
436  LSM6DSL_CTRL6_FTYPE1 = 0x02,
437  _LSM6DSL_CTRL6_FTYPE_MASK = 3,
438  _LSM6DSL_CTRL6_FTYPE_SHIFT = 0,
439 
440  // 0x04 reserved
441 
442  LSM6DSL_CTRL6_USR_OFF_W = 0x08,
443 
444  LSM6DSL_CTRL6_XL_HM_MODE = 0x10,
445  LSM6DSL_CTRL6_LVL2_EN = 0x20,
446  LSM6DSL_CTRL6_LVLEN = 0x40,
447  LSM6DSL_CTRL6_TRIG_EN = 0x80,
448  } LSM6DSL_CTRL6_BITS_T;
449 
453  typedef enum {
454  LSM6DSL_FTYPE_00 = 0,
455  LSM6DSL_FTYPE_01 = 1,
456  LSM6DSL_FTYPE_10 = 2,
457  LSM6DSL_FTYPE_11 = 3,
458  } LSM6DSL_FTYPE_T;
459 
463  typedef enum {
464  // 0x01-0x02 reserved
465 
466  LSM6DSL_CTRL7_G_ROUNDING_STATUS = 0x04,
467 
468  // 0x08 reserved
469 
470  LSM6DSL_CTRL7_G_HPM0 = 0x10,
471  LSM6DSL_CTRL7_G_HPM1 = 0x20,
472  _LSM6DSL_CTRL7_G_HPM_MASK = 3,
473  _LSM6DSL_CTRL7_G_HPM_SHIFT = 4,
474 
475  LSM6DSL_CTRL7_G_HP_EN = 0x40,
476  LSM6DSL_CTRL7_G_HM_MODE = 0x80,
477  } LSM6DSL_CTRL7_G_BITS_T;
478 
482  typedef enum {
483  LSM6DSL_G_HPM_16MHZ = 0, // 16 mHZ
484  LSM6DSL_G_HPM_65MHZ = 1,
485  LSM6DSL_G_HPM_260MHZ = 2,
486  LSM6DSL_G_HPM_1_04HZ = 3, // 1.04HZ
487  } LSM6DSL_G_HPM_T;
488 
492  typedef enum {
493  LSM6DSL_CTRL8_XL_LOW_PASS_ON_6D = 0x01,
494 
495  // 0x02 reserved
496 
497  LSM6DSL_CTRL8_XL_HP_SLOPE_EN = 0x04,
498 
499  LSM6DSL_CTRL8_INPUT_COMPOSITE = 0x08,
500 
501  LSM6DSL_CTRL8_HP_REF_MODE = 0x10,
502 
503  LSM6DSL_CTRL8_XL_HPCF0 = 0x20,
504  LSM6DSL_CTRL8_XL_HPCF1 = 0x40,
505  _LSM6DSL_CTRL8_XL_HPCF_MASK = 3,
506  _LSM6DSL_CTRL8_XL_HPCF_SHIFT = 5,
507 
508  LSM6DSL_CTRL8_XL_LPF2_EN = 0x80,
509  } LSM6DSL_CTRL8_XL_BITS_T;
510 
514  typedef enum {
515  // 0x01-0x02 reserved
516 
517  LSM6DSL_CTRL9_XL_SOFT_EN = 0x04,
518 
519  // 0x08 reserved
520 
521  LSM6DSL_CTRL9_XL_DEN_XL_G = 0x10,
522  LSM6DSL_CTRL9_XL_DEN_Z = 0x20,
523  LSM6DSL_CTRL9_XL_DEN_Y = 0x40,
524  LSM6DSL_CTRL9_XL_DEN_X = 0x80,
525  } LSM6DSL_CTRL9_XL_BITS_T;
526 
530  typedef enum {
531  LSM6DSL_CTRL10_C_SIGN_MOT_EN = 0x01,
532  LSM6DSL_CTRL10_C_PEDO_RST_STEP = 0x02,
533  LSM6DSL_CTRL10_C_FUNC_EN = 0x04,
534  LSM6DSL_CTRL10_C_TILT_EN = 0x08,
535  LSM6DSL_CTRL10_C_PEDO_EN = 0x10,
536  LSM6DSL_CTRL10_C_TIMER_EN = 0x20,
537 
538  // 0x40 reserved
539 
540  LSM6DSL_CTRL10_C_WRIST_TILT_EN = 0x80,
541  } LSM6DSL_CTRL10_G_BITS_T;
542 
546  typedef enum {
547  LSM6DSL_MASTER_CONFIG_MASTER_ON = 0x01,
548  LSM6DSL_MASTER_CONFIG_IRON_EN = 0x02,
549  LSM6DSL_MASTER_CONFIG_PASS_THROUGH_MODE = 0x04,
550  LSM6DSL_MASTER_CONFIG_PULL_UP_EN = 0x08,
551  LSM6DSL_MASTER_CONFIG_START_CONFIG = 0x10,
552 
553  // 0x20 reserved
554 
555  LSM6DSL_MASTER_CONFIG_DATA_VALID_SEL_FIFO = 0x40,
556  LSM6DSL_MASTER_CONFIG_DRDY_ON_INT1 = 0x80,
557  } LSM6DSL_MASTER_CONFIG_BITS_T;
558 
562  typedef enum {
563  LSM6DSL_WAKE_UP_SRC_Z_WU = 0x01,
564  LSM6DSL_WAKE_UP_SRC_Y_WU = 0x02,
565  LSM6DSL_WAKE_UP_SRC_X_WU = 0x04,
566  LSM6DSL_WAKE_UP_SRC_WU_IA = 0x08,
567  LSM6DSL_WAKE_UP_SRC_SLEEP_STATE_IA = 0x10,
568  LSM6DSL_WAKE_UP_SRC_FF_AA = 0x20,
569 
570  // 0x40-0x80 reserved
571  } LSM6DSL_WAKE_UP_SRC_BITS_T;
572 
576  typedef enum {
577  LSM6DSL_TAP_SRC_Z_TAP = 0x01,
578  LSM6DSL_TAP_SRC_Y_TAP = 0x02,
579  LSM6DSL_TAP_SRC_X_TAP = 0x04,
580  LSM6DSL_TAP_SRC_TAP_SIGN = 0x08,
581  LSM6DSL_TAP_SRC_DOUBLE_TAP = 0x10,
582  LSM6DSL_TAP_SRC_SINGLE_TAP = 0x20,
583  LSM6DSL_TAP_SRC_TAP_IA = 0x40,
584 
585  // 0x80 reserved
586  } LSM6DSL_TAP_SRC_BITS_T;
587 
591  typedef enum {
592  LSM6DSL_D6D_SRC_XL = 0x01,
593  LSM6DSL_D6D_SRC_XH = 0x02,
594  LSM6DSL_D6D_SRC_YL = 0x04,
595  LSM6DSL_D6D_SRC_YH = 0x08,
596  LSM6DSL_D6D_SRC_ZL = 0x10,
597  LSM6DSL_D6D_SRC_ZH = 0x20,
598  LSM6DSL_D6D_SRC_D6D_IA = 0x40,
599 
600  // 0x80 reserved
601  } LSM6DSL_D6D_SRC_BITS_T;
602 
606  typedef enum {
607  LSM6DSL_STATUS_XLDA = 0x01, // acc data avail
608  LSM6DSL_STATUS_GDA = 0x02, // gyr data avail
609  LSM6DSL_STATUS_TDA = 0x04, // temp data avail
610 
611  // 0x08-0x80 reserved
612  } LSM6DSL_STATUS_BITS_T;
613 
617  typedef enum {
618  LSM6DSL_FUNC_SRC1_SENSORHUB_END_OP = 0x01,
619  LSM6DSL_FUNC_SRC1_SI_END_OP = 0x02,
620 
621  LSM6DSL_FUNC_SRC1_HI_FAIL = 0x04,
622 
623  LSM6DSL_FUNC_SRC1_STEP_OVERFLOW = 0x08,
624  LSM6DSL_FUNC_SRC1_STEP_DETECTED = 0x10,
625  LSM6DSL_FUNC_SRC1_TILT_IA = 0x20,
626  LSM6DSL_FUNC_SRC1_SIGN_MOTION_IA = 0x40,
627  LSM6DSL_FUNC_SRC1_STEP_COUNT_DELTA_IA = 0x80,
628  } LSM6DSL_FUNC_SRC1_BITS_T;
629 
633  typedef enum {
634  LSM6DSL_FUNC_SRC2_WRIST_TILT_IA = 0x01,
635 
636  // 0x02-0x04 reserved
637 
638  LSM6DSL_FUNC_SRC2_SLAVE0_NACK = 0x08,
639  LSM6DSL_FUNC_SRC2_SLAVE1_NACK = 0x10,
640  LSM6DSL_FUNC_SRC2_SLAVE2_NACK = 0x20,
641  LSM6DSL_FUNC_SRC2_SLAVE3_NACK = 0x40,
642 
643  // 0x80 reserved
644  } LSM6DSL_FUNC_SRC2_BITS_T;
645 
650  typedef enum {
651  LSM6DSL_MD1_CFG_TIMER = 0x01,
652  LSM6DSL_MD1_CFG_TILT = 0x02,
653  LSM6DSL_MD1_CFG_6D = 0x04,
654  LSM6DSL_MD1_CFG_DOUBLE_TAP = 0x08,
655  LSM6DSL_MD1_CFG_FF = 0x10,
656  LSM6DSL_MD1_CFG_WU = 0x20,
657  LSM6DSL_MD1_CFG_SINGLE_TAP = 0x40,
658  LSM6DSL_MD1_CFG_INACT_STATE = 0x80,
659  } LSM6DSL_MD1_CFG_BITS_T;
660 
665  typedef enum {
666  LSM6DSL_MD2_CFG_IRON = 0x01,
667  LSM6DSL_MD2_CFG_TILT = 0x02,
668  LSM6DSL_MD2_CFG_6D = 0x04,
669  LSM6DSL_MD2_CFG_DOUBLE_TAP = 0x08,
670  LSM6DSL_MD2_CFG_FF = 0x10,
671  LSM6DSL_MD2_CFG_WU = 0x20,
672  LSM6DSL_MD2_CFG_SINGLE_TAP = 0x40,
673  LSM6DSL_MD2_CFG_INACT_STATE = 0x80,
674  } LSM6DSL_MD2_CFG_BITS_T;
675 
676  // interrupt selection for installISR() and uninstallISR()
677  typedef enum {
678  LSM6DSL_INTERRUPT_INT1,
679  LSM6DSL_INTERRUPT_INT2
680  } LSM6DSL_INTERRUPT_PINS_T;
681 
682 
683 #ifdef __cplusplus
684 }
685 #endif
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