upm  1.7.1
Sensor/Actuator repository for libmraa (v2.0.0)
mcp2515_regs.h
1 /*
2  * Author: Jon Trulson <jtrulson@ics.com>
3  * Copyright (c) 2016 Intel Corporation.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
20  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 #pragma once
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
30 // maximum number of bytes we can send/receive
31 #define MCP2515_MAX_PAYLOAD_DATA (8)
32 
33 // This includes SIDH, SIDL, EID8, EID0, DLC, and 8 payload bytes.
34 // This represents the non-control components of the RX and TX
35 // buffers.
36 #define MCP2515_MAX_PKT_DATA (13)
37 // Now we break them out for clarity. These are offsets into a
38 // transmitted or received packet.
39 #define MCP2515_PKT_SIDH (0)
40 #define MCP2515_PKT_SIDL (1)
41 #define MCP2515_PKT_EID8 (2)
42 #define MCP2515_PKT_EID0 (3)
43 #define MCP2515_PKT_DLC (4)
44 #define MCP2515_PKT_D0 (5)
45 #define MCP2515_PKT_D1 (6)
46 #define MCP2515_PKT_D2 (7)
47 #define MCP2515_PKT_D3 (8)
48 #define MCP2515_PKT_D4 (9)
49 #define MCP2515_PKT_D5 (10)
50 #define MCP2515_PKT_D6 (11)
51 #define MCP2515_PKT_D7 (12)
52 
53 // The number of bytes that make up an ID (SIDH, SIDL, EID8, EID0)
54 #define MCP2515_MAX_ID_BYTES (4)
55 
56  // 4 byte SIDH, SIDL, SID8, SID0 id. This is used only for
57  // converting back and forth from an integer and 4-byte device
58  // representation of a standard or extended ID.
59  typedef union {
60  uint8_t data[MCP2515_MAX_ID_BYTES];
61  struct {
62  uint8_t SIDH;
63  uint8_t SIDL;
64  uint8_t EID8;
65  uint8_t EID0;
66  };
67  } MCP2515_ID_T;
68 
69  // 13 byte packet starting at SIDH. This is used to represent
70  // packets for transmission and reception.
71  typedef union {
72  uint8_t data[MCP2515_MAX_PKT_DATA];
73  struct {
74  uint8_t SIDH; // Id data
75  uint8_t SIDL;
76  uint8_t EID8;
77  uint8_t EID0;
78  uint8_t DLC; // DLC (data length)
79  uint8_t D0; // start of 8 byte (max) payload
80  uint8_t D1;
81  uint8_t D2;
82  uint8_t D3;
83  uint8_t D4;
84  uint8_t D5;
85  uint8_t D6;
86  uint8_t D7;
87  };
88  } MCP2515_PKT_T;
89 
90  // A received message. This includes the packet, and some decoded
91  // data (rtr, ext, id, etc.
92  typedef struct {
93  int id;
94  bool rtr;
95  bool ext;
96  int filter_num;
97  int len;
98  MCP2515_PKT_T pkt;
99  } MCP2515_MSG_T;
100 
101  // Registers
102  typedef enum {
103  // 5 RX filters, each composed of SIDH, SIDL, EID8, EID0. We
104  // only specify the leading (SIDH) address here.
105 
106  // first two filters are associated with rxb0
107  MCP2515_REG_FILTER0 = 0x00,
108  MCP2515_REG_FILTER1 = 0x04,
109  // remaining 4 filters are associated with rxb1
110  MCP2515_REG_FILTER2 = 0x08,
111  MCP2515_REG_FILTER3 = 0x10,
112  MCP2515_REG_FILTER4 = 0x14,
113  MCP2515_REG_FILTER5 = 0x18,
114 
115  // 2 RX filter mask registers, like above, we only specify the
116  // SIDH address
117 
118  // associated with rxb0
119  MCP2515_REG_MASK0 = 0x20,
120  // associated with rxb1
121  MCP2515_REG_MASK1 = 0x24,
122 
123  MCP2515_REG_BFPCTL = 0x0c,
124  MCP2515_REG_TXRTSCTRL = 0x0d, // tx ready-to-send
125 
126  // CANSTAT and CANCTRL are aliased in several locations to
127  // make it easier to get maximum data using burst reads. In
128  // reality, they are the same register, but we list them all
129  // anyway for completeness.
130 
131  // CANSTAT and aliases
132  MCP2515_REG_CANSTAT = 0x0e,
133  MCP2515_REG_CANSTAT_0 = 0x0e, // same as CANSTAT
134 
135  MCP2515_REG_CANSTAT_1 = 0x1e, // rest of the aliases
136  MCP2515_REG_CANSTAT_2 = 0x2e,
137  MCP2515_REG_CANSTAT_3 = 0x3e,
138  MCP2515_REG_CANSTAT_4 = 0x4e,
139  MCP2515_REG_CANSTAT_5 = 0x5e,
140  MCP2515_REG_CANSTAT_6 = 0x6e,
141  MCP2515_REG_CANSTAT_7 = 0x7e,
142 
143  // CANCTRL and aliases
144  MCP2515_REG_CANCTRL = 0x0f,
145  MCP2515_REG_CANCTRL_0 = 0x0f, // same as CANCTRL
146 
147  MCP2515_REG_CANCTRL_1 = 0x1f, // rest of the aliases
148  MCP2515_REG_CANCTRL_2 = 0x2f,
149  MCP2515_REG_CANCTRL_3 = 0x3f,
150  MCP2515_REG_CANCTRL_4 = 0x4f,
151  MCP2515_REG_CANCTRL_5 = 0x5f,
152  MCP2515_REG_CANCTRL_6 = 0x6f,
153  MCP2515_REG_CANCTRL_7 = 0x7f,
154 
155  MCP2515_REG_TEC = 0x1c, // tx error count
156  MCP2515_REG_REC = 0x1d, // rx error count
157 
158  MCP2515_REG_CNF3 = 0x28, // configuration bytes
159  MCP2515_REG_CNF2 = 0x29,
160  MCP2515_REG_CNF1 = 0x2a,
161 
162  MCP2515_REG_CANINTE = 0x2b, // intr enables
163  MCP2515_REG_CANINTF = 0x2c, // intr flags
164 
165  MCP2515_REG_EFLG = 0x2a, // error flags
166 
167  // Start of the buffer reg ranges for tx and rx buffers.
168  // There are 3 transmit buffers and 2 rx buffers. You can
169  // read and write 16 bytes (0x0f) starting at these locations
170  // to set and/get buffer control bits, message ids, msg
171  // content, and CANSTAT and CANCTRL regs in one bus transaction.
172 
173  // See the datasheet page 61
174  MCP2515_REG_TXB0CTRL = 0x30, // tx buffer 0 ctrl
175  MCP2515_REG_TXB1CTRL = 0x40, // tx buffer 1 ctrl
176  MCP2515_REG_TXB2CTRL = 0x50, // tx buffer 2 ctrl
177 
178  MCP2515_REG_RXB0CTRL = 0x60, // rx buffer 0 ctrl
179  MCP2515_REG_RXB1CTRL = 0x70 // rx buffer 1 ctrl
180  } MCP2515_REG_T;
181 
182  // MCP2515_REG_CANCTRL bits
183  typedef enum {
184  MCP2515_CANCTRL_CLKPRE0 = 0x01,
185  MCP2515_CANCTRL_CLKPRE1 = 0x02,
186  _MCP2515_CANCTRL_CLKPRE_MASK = 3,
187  _MCP2515_CANCTRL_CLKPRE_SHIFT = 0,
188 
189  MCP2515_CANCTRL_CLKEN = 0x04, //enable CLKOUT pin
190 
191  MCP2515_CANCTRL_OSM = 0x08, // one shot mode
192 
193  MCP2515_CANCTRL_ABAT = 0x10, // abort all pending tx
194 
195  MCP2515_CANCTRL_REQOP0 = 0x20, // request new operating mode
196  MCP2515_CANCTRL_REQOP1 = 0x40,
197  MCP2515_CANCTRL_REQOP2 = 0x80,
198  _MCP2515_CANCTRL_REQOP_MASK = 7,
199  _MCP2515_CANCTRL_REQOP_SHIFT = 5,
200  } MCP2515_CANCTRL_BITS_T;
201 
202  // MCP2515_CLKPRE values
203  typedef enum {
204  MCP2515_CLKPRE_DIV1 = 0, // sysclk/1
205  MCP2515_CLKPRE_DIV2 = 1, // sysclk/2
206  MCP2515_CLKPRE_DIV4 = 2, // sysclk/4
207  MCP2515_CLKPRE_DIV8 = 3 // sysclk/8
208  } MCP2515_CLKPRE_T;
209 
210  // MCP2515_OPMODE values. These are the same for the CANCTRL_REQOP and
211  // CANSTAT_OPMODE bitfields.
212  typedef enum {
213  MCP2515_OPMODE_NORMAL = 0,
214  MCP2515_OPMODE_SLEEP = 1,
215  MCP2515_OPMODE_LOOPBACK = 2,
216  MCP2515_OPMODE_LISTENONLY = 3,
217  MCP2515_OPMODE_CONFIG = 4
218  } MCP2515_OPMODE_T;
219 
220  // MCP2515_REG_CANSTAT bits
221  typedef enum {
222  // 0x01 reserved
223 
224  MCP2515_CANSTAT_ICOD0 = 0x02, // intr flag code
225  MCP2515_CANSTAT_ICOD1 = 0x04,
226  MCP2515_CANSTAT_ICOD2 = 0x08,
227  _MCP2515_CANSTAT_ICOD_MASK = 7,
228  _MCP2515_CANSTAT_ICOD_SHIFT = 1,
229 
230  // 0x10 reserved
231 
232  MCP2515_CANSTAT_OPMODE0 = 0x20, // request new operating mode
233  MCP2515_CANSTAT_OPMODE1 = 0x40,
234  MCP2515_CANSTAT_OPMODE2 = 0x80,
235  _MCP2515_CANSTAT_OPMODE_MASK = 7,
236  _MCP2515_CANSTAT_OPMODE_SHIFT = 5,
237  } MCP2515_CANSTAT_BITS_T;
238 
239  // MCP2515_REG_BFPCTL bits, Buffer Pin Control
240  typedef enum {
241  MCP2515_BFPCTL_B0BFM = 0x01, // opmode bit
242  MCP2515_BFPCTL_B1BFM = 0x02,
243 
244  MCP2515_BFPCTL_B0BFE = 0x04, // func enable bit
245  MCP2515_BFPCTL_B1BFE = 0x08,
246 
247  MCP2515_BFPCTL_B0BFS = 0x10, // pin state (output mode only)
248  MCP2515_BFPCTL_B1BFS = 0x20,
249 
250  // 0x40-0x080 reserved
251  } MCP2515_BFPCTL_BITS_T;
252 
253  // MCP2515_REG_TXRTSCTRL bits, TX RTS pin control
254  typedef enum {
255  MCP2515_TXRTSCTRL_B0RTSM = 0x01, // pin mode
256  MCP2515_TXRTSCTRL_B1RTSM = 0x02,
257  MCP2515_TXRTSCTRL_B2RTSM = 0x04,
258 
259  MCP2515_TXRTSCTRL_B0RTS = 0x08, // pin state when in
260  // input mode
261  MCP2515_TXRTSCTRL_B1RTS = 0x10,
262  MCP2515_TXRTSCTRL_B2RTS = 0x20,
263 
264  // 0x40-0x80 reserved
265  } MCP2515_TXRTSCTRL_BITS_T;
266 
267  // MCP2515_REG_EFLG bits, Error flags
268  typedef enum {
269  MCP2515_EFLG_EWARN = 0x01, // error warning (TEC/REC > 96)
270  MCP2515_EFLG_RXWAR = 0x02, // rx warning (REC > 96)
271  MCP2515_EFLG_TXWAR = 0x04, // tx warning (REC > 96)
272 
273  MCP2515_EFLG_RXEP = 0x08, // rx error-passive
274  MCP2515_EFLG_TXEP = 0x10, // tx error-passive
275 
276  MCP2515_EFLG_TXBO = 0x20, // tx bus off
277 
278  MCP2515_EFLG_RX0OVR = 0x40, // rx buf 0 overflow
279  MCP2515_EFLG_RX1OVR = 0x80, // rx buf 1 overflow
280  } MCP2515_EFLG_BITS_T;
281 
282  // MCP2515_REG_CANINTE and MCP2515_REG_CANINTF bits, interrupt
283  // enables and flags. We use the same enum here as the two regs
284  // have the same bits.
285  typedef enum {
286  MCP2515_CANINT_RX0I = 0x01, // rx buf 0 full
287  MCP2515_CANINT_RX1I = 0x02, // rx buf 1 full
288 
289  MCP2515_CANINT_TX0I = 0x04, // tx buf 1 empty
290  MCP2515_CANINT_TX1I = 0x08, // tx buf 2 empty
291  MCP2515_CANINT_TX2I = 0x10, // tx buf 3 empty
292 
293  MCP2515_CANINT_ERRI = 0x20, // error intr
294  MCP2515_CANINT_WAKI = 0x40, // wakeup intr
295 
296  MCP2515_CANINT_MERR = 0x80 // msg error
297  } MCP2515_CANINT_BITS_T;
298 
299  // MCP2515_REG_TXBCTRL, TX control for tx buffers 0 (0x30), 1
300  // (0x40), and 2 (0x50)
301  typedef enum {
302  MCP2515_TXBCTRL_TXP0 = 0x01, // message priority
303  MCP2515_TXBCTRL_TXP1 = 0x02,
304  _MCP2515_TXBCTRL_TXP_MASK = 3,
305  _MCP2515_TXBCTRL_TXP_SHIFT = 0,
306 
307  // 0x04 reserved
308 
309  MCP2515_TXBCTRL_TXREQ = 0x08, // tx request
310  MCP2515_TXBCTRL_TXERR = 0x10, // tx error detected
311  MCP2515_TXBCTRL_MLOA = 0x20, // msg lost arbitration
312  MCP2515_TXBCTRL_ABTF = 0x40 // msg aborted flag
313 
314  // 0x80 reserved
315  } MCP2515_TXBCTRL_BITS_T;
316 
317  // MCP2515_TXBCTRL_TXP priority values
318  typedef enum {
319  MCP2515_TXP_LOWEST = 0,
320  MCP2515_TXP_LOW = 1,
321  MCP2515_TXP_HIGH = 2,
322  MCP2515_TXP_HIGHEST = 3
323  } MCP2515_TXP_T;
324 
325  // MCP2515_TXBDLC bits, (addresses 0x35, 0x45, 0x55)
326  typedef enum {
327  MCP2515_TXBDLC_DLC0 = 0x01, // data length code
328  MCP2515_TXBDLC_DLC1 = 0x02, // max is 8 bytes
329  MCP2515_TXBDLC_DLC2 = 0x04,
330  MCP2515_TXBDLC_DLC3 = 0x08,
331  _MCP2515_TXBDLC_MASK = 15,
332  _MCP2515_TXBDLC_SHIFT = 0,
333 
334  // 0x10-0x20 reserved
335 
336  MCP2515_TXBDLC_RTR = 0x40, // remote
337  // transmission
338  // request bit
339 
340  // 0x80 reserved
341  } MCP2515_TXBDLC_BITS_T;
342 
343  // MCP2515_REG_RXB0CTRL, RX control for rx buffer 0 (0x60)
344  typedef enum {
345  MCP2515_RXB0CTRL_FILHIT = 0x01, // which filter was hit
346 
347  MCP2515_RXB0CTRL_BUKT1 = 0x02, // readonly version of BUKT
348  MCP2515_RXB0CTRL_BUKT = 0x04, // rollover enable (to rx1)
349 
350  MCP2515_RXB0CTRL_RXRTR = 0x08, // RTR request
351 
352  // 0x10 reserved
353 
354  MCP2515_RXB0CTRL_RXMODE0 = 0x20, // rx buf mode bits
355  MCP2515_RXB0CTRL_RXMODE1 = 0x40,
356  _MCP2515_RXB0CTRL_RXMODE_MASK = 3,
357  _MCP2515_RXB0CTRL_RXMODE_SHIFT = 5
358 
359  // 0x80 reserved
360  } MCP2515_RXB0CTRL_BITS_T;
361 
362  // These values determine whether the filters are used and what
363  // kinds of messages to accept. They are the same for both rx
364  // buffers.
365  typedef enum {
366  MCP2515_RXMODE_ANY_FILTER = 0, // std/ext based on filter
367  MCP2515_RXMODE_STANDARD_FILTER = 1, // standard only, filter
368  MCP2515_RXMODE_EXTENDED_FILTER = 2, // extended only, filter
369  MCP2515_RXMODE_ANY_NOFILTER = 3 // any, no filter
370  } MCP2515_RXMODE_T;
371 
372  // MCP2515_REG_RXB1CTRL, RX control for rx buffer 1 (0x70)
373  typedef enum {
374  MCP2515_RXB1CTRL_FILHIT0 = 0x01, // which filter was hit
375  MCP2515_RXB1CTRL_FILHIT1 = 0x02, // for a rollover, this can
376  MCP2515_RXB1CTRL_FILHIT2 = 0x04, // be filter 0 or 1 too.
377  _MCP2515_RXB1CTRL_FILHIT_MASK = 7,
378  _MCP2515_RXB1CTRL_FILHIT_SHIFT = 0,
379 
380  MCP2515_RXB1CTRL_RXRTR = 0x08, // RTR request
381 
382  // 0x10 reserved
383 
384  MCP2515_RXB1CTRL_RXMODE0 = 0x20, // rx buf mode bits
385  MCP2515_RXB1CTRL_RXMODE1 = 0x40,
386  _MCP2515_RXB1CTRL_RXMODE_MASK = 3,
387  _MCP2515_RXB1CTRL_RXMODE_SHIFT = 5
388 
389  // 0x80 reserved
390  } MCP2515_RXB1CTRL_BITS_T;
391 
392  // MCP2515_RXB1CTRL_FILHIT values for rx buffer 1
393  typedef enum {
394  MCP2515_FILHIT_F0 = 0, // filter 0 hit (only if bukt)
395  MCP2515_FILHIT_F1 = 1, // filter 1 hit (only if bukt)
396  MCP2515_FILHIT_F2 = 2, // filter 2 hit
397  MCP2515_FILHIT_F3 = 3,
398  MCP2515_FILHIT_F4 = 4,
399  MCP2515_FILHIT_F5 = 5
400  } MCP2515_FILHIT_T;
401 
402  // Valid CANBUS speeds. These are precomputed and represented in
403  // a table in mcp2515.c. It is a requirement that the enum values
404  // below correspond to the indexes in the speed table. Keep them
405  // in sync! Add any new values to the end of this enum, and to
406  // the corresponding table in mcp2515.c.
407  //
408  // These values are valid only for 16Mhz clocks.
409  typedef enum {
410  MCP2515_SPEED_5KBPS = 0,
411  MCP2515_SPEED_10KBPS = 1,
412  MCP2515_SPEED_20KBPS = 2,
413  MCP2515_SPEED_25KBPS = 3,
414  MCP2515_SPEED_31_25KBPS = 4, // 31.25kbps
415  MCP2515_SPEED_33KBPS = 5,
416  MCP2515_SPEED_40KBPS = 6,
417  MCP2515_SPEED_50KBPS = 7,
418  MCP2515_SPEED_80KBPS = 8,
419  MCP2515_SPEED_83KBPS = 9,
420 
421  MCP2515_SPEED_95KBPS = 10,
422  MCP2515_SPEED_100KBPS = 11,
423  MCP2515_SPEED_125KBPS = 12,
424  MCP2515_SPEED_200KBPS = 13,
425  MCP2515_SPEED_250KBPS = 14,
426  MCP2515_SPEED_500KBPS = 15,
427  MCP2515_SPEED_666KBPS = 16,
428  MCP2515_SPEED_1000KBPS = 17
429  } MCP2515_SPEED_T;
430 
431  // MCP2515_RXBDLC bits, (addresses 0x65, 0x75)
432  typedef enum {
433  MCP2515_RXBDLC_DLC0 = 0x01, // data length code
434  MCP2515_RXBDLC_DLC1 = 0x02, // max is 8 bytes
435  MCP2515_RXBDLC_DLC2 = 0x04,
436  MCP2515_RXBDLC_DLC3 = 0x08,
437  _MCP2515_RXBDLC_MASK = 15,
438  _MCP2515_RXBDLC_SHIFT = 0,
439 
440  // 0x10-0x20 reserved
441 
442  MCP2515_RXBDLC_RTR = 0x40, // remote
443  // transmission
444  // request bit, if
445  // extended id
446 
447  // 0x80 reserved
448  } MCP2515_RXBDLC_BITS_T;
449 
450  // SPI commands - these are commands sent to the device to start
451  // certain operations. The datasheet specifies that after CS is
452  // active, the first byte must be the command byte. It is not
453  // possible to send multiple commands in a single transaction
454  // (a CS On/CS Off sequence).
455  typedef enum {
456  MCP2515_CMD_RESET = 0xc0,
457 
458  MCP2515_CMD_READ = 0x03,
459 
460  // These commands allows the specification of a read buffer.
461  // The real command is 0x90. The lower nibble is 0mn0,
462  // where m and n specify the 4 locations to start reading
463  // from. In this list, we will enumerate all of them.
464  //
465  // n m cmd real hex addr
466  // ------------------------------
467  // 0 0 RXB0SIDH 0x61
468  // 0 1 RXB0D0 0x66
469  // 1 0 RXB1SIDH 0x71
470  // 1 1 RXB1D0 0x76
471  MCP2515_CMD_READ_RXBUF_RXB0SIDH = 0x90,
472  MCP2515_CMD_READ_RXBUF_RXB0D0 = 0x92,
473  MCP2515_CMD_READ_RXBUF_RXB1SIDH = 0x94,
474  MCP2515_CMD_READ_RXBUF_RXB1D0 = 0x96,
475 
476  MCP2515_CMD_WRITE = 0x02,
477 
478  // This command allows speedier loading of tx buffer contents.
479  // The lower nibble is 0b0abc, where abc specifies 6 location
480  // addresses to start writing to. This works similarly to the
481  // READ_RXBUF_* commands.
482  //
483  // a b c cmd real hex addr
484  // ----------------------------------
485  // 0 0 0 TXB0SIDH 0x31
486  // 0 0 1 TXB0D0 0x36
487  // 0 1 0 TXB1SIDH 0x41
488  // 0 1 1 TXB1D0 0x46
489  // 1 0 0 TXB2SIDH 0x51
490  // 1 0 1 TXB2D0 0x56
491  MCP2515_CMD_LOAD_TXBUF_TXB0SIDH = 0x40,
492  MCP2515_CMD_LOAD_TXBUF_TXB0D0 = 0x41,
493  MCP2515_CMD_LOAD_TXBUF_TXB1SIDH = 0x42,
494  MCP2515_CMD_LOAD_TXBUF_TXB1D0 = 0x43,
495  MCP2515_CMD_LOAD_TXBUF_TXB2SIDH = 0x44,
496  MCP2515_CMD_LOAD_TXBUF_TXB2D0 = 0x45,
497 
498  // Request to Send. This is a quick way to request the
499  // sending of tx buffers without having to do a
500  // read/modify/write register sequence. The lower 3 bits
501  // indicate which buffer(s) to setup for transmission.
502  //
503  // 0x8n Where n is 0b0xxx. bit 0 is for txb 0, bit 1 for txb 1
504  // and bit 2 for txb 2.
505  MCP2515_CMD_RTS = 0x80,
506  MCP2515_CMD_RTS_BUFFER0 = 0x81,
507  MCP2515_CMD_RTS_BUFFER1 = 0x82,
508  MCP2515_CMD_RTS_BUFFER2 = 0x84,
509 
510  // return status bits for rx and tx. See MCP2515_RDSTATUS_BITS_T.
511  MCP2515_CMD_READ_STATUS = 0xa0,
512 
513  // returns information on which filters have been matched.
514  // See MCP2515_RXSTATUS_BITS_T.
515  MCP2515_CMD_RX_STATUS = 0xb0,
516 
517  // This command allows for certain registers to have certain
518  // bit(s) modified w/o going through a read/modify/write cycle
519  // of the whole register. See the datasheet - only certain
520  // registers can be used with this command.
521  //
522  // The format for this command is: cmd, addr, mask, value
523  MCP2515_CMD_BIT_MODIFY = 0x05
524  } MCP2515_CMD_T;
525 
526  // This bitfield is the contents of the byte returned from a
527  // CMD_READ_STATUS command.
528  typedef enum {
529  MCP2515_RDSTATUS_RX0IF = 0x01, // rx buf 0 full IF
530  MCP2515_RDSTATUS_RX1IF = 0x02, // rx buf 1 full IF
531  MCP2515_RDSTATUS_TXB0REQ = 0x04, // TX buf 0 req bit
532  MCP2515_RDSTATUS_TXB0IF = 0x08, // TX buf 0 empty IF
533  MCP2515_RDSTATUS_TXB1REQ = 0x10, // TX buf 1 req bit
534  MCP2515_RDSTATUS_TXB1IF = 0x20, // TX buf 1 empty IF
535  MCP2515_RDSTATUS_TXB2REQ = 0x40, // TX buf 2 req bit
536  MCP2515_RDSTATUS_TXB2IF = 0x80 // TX buf 2 empty IF
537  } MCP2515_RDSTATUS_BITS_T;
538 
539  // This bitfield is the contents of the byte returned from a
540  // CMD_READ_RX_STATUS command.
541  typedef enum {
542  MCP2515_RXSTATUS_FILTERMATCH0 = 0x01,
543  MCP2515_RXSTATUS_FILTERMATCH1 = 0x02,
544  MCP2515_RXSTATUS_FILTERMATCH2 = 0x04,
545  _MCP2515_RXSTATUS_FILTERMATCH_MASK = 7,
546  _MCP2515_RXSTATUS_FILTERMATCH_SHIFT = 0,
547 
548  MCP2515_RXSTATUS_MSGTYPE0 = 0x08,
549  MCP2515_RXSTATUS_MSGTYPE1 = 0x10,
550  _MCP2515_RXSTATUS_MSGTYPE_MASK = 3,
551  _MCP2515_RXSTATUS_MSGTYPE_SHIFT = 3,
552 
553  // 0x20 is not mentioned in the DS
554 
555  MCP2515_RXSTATUS_RXMSG0 = 0x40,
556  MCP2515_RXSTATUS_RXMSG1 = 0x80,
557  _MCP2515_RXSTATUS_RXMSG_MASK = 3,
558  _MCP2515_RXSTATUS_RXMSG_SHIFT = 6
559  } MCP2515_RXSTATUS_BITS_T;
560 
561  // MCP2515_RXSTATUS_FILTERMATCH values
562  typedef enum {
563  MCP2515_FILTERMATCH_RXF0 = 0,
564  MCP2515_FILTERMATCH_RXF1 = 1,
565  MCP2515_FILTERMATCH_RXF2 = 2,
566  MCP2515_FILTERMATCH_RXF3 = 3,
567  MCP2515_FILTERMATCH_RXF4 = 4,
568  MCP2515_FILTERMATCH_RXF5 = 5,
569  MCP2515_FILTERMATCH_RXF0_ROLLOVER = 6,
570  MCP2515_FILTERMATCH_RXF1_ROLLOVER = 7
571  } MCP2515_FILTERMATCH_T;
572 
573  // MCP2515_RXSTATUS_MSGTYPE values
574  typedef enum {
575  MCP2515_MSGTYPE_STD = 0, // standard
576  MCP2515_MSGTYPE_STDRF = 1, // standard remote frame
577  MCP2515_MSGTYPE_EXT = 2, // extended
578  MCP2515_MSGTYPE_EXTRF = 3 // extended remote frame
579  } MCP2515_MSGTYPE_T;
580 
581  // MCP2515_RXSTATUS_RXMSG values
582  typedef enum {
583  MCP2515_RXMSG_NONE = 0, // no msg
584  MCP2515_RXMSG_RXB0 = 1, // msg in rxb0
585  MCP2515_RXMSG_RXB1 = 2, // msg in rxb1
586  MCP2515_RXMSG_BOTH = 3 // msg in both
587  } MCP2515_RXMSG_T;
588 
589  // we spell out the SIDL registers as they contain the EXIDE bit.
590  // The others (SIDL, EID0 and EID8 just contain their respective
591  // ID bits.
592  typedef enum {
593  MCP2515_SIDL_EID16 = 0x01,
594  MCP2515_SIDL_EID17 = 0x02,
595 
596  // 0x04 reserved
597 
598  MCP2515_SIDL_EXIDE = 0x08,
599 
600  // 0x10 reserved
601 
602  MCP2515_SIDL_SID0 = 0x20,
603  MCP2515_SIDL_SID1 = 0x40,
604  MCP2515_SIDL_SID2 = 0x80
605  } MCP2515_SIDL_T;
606 
607  // An enum to specify one of the 3 TX buffers
608  typedef enum {
609  MCP2515_TX_BUFFER0 = 0,
610  MCP2515_TX_BUFFER1 = 1,
611  MCP2515_TX_BUFFER2 = 2,
612  // special value indicating no buffers
613  MCP2515_TX_NO_BUFFERS = 255
614  } MCP2515_TX_BUFFER_T;
615 
616  // An enum to specify one of the 2 rx buffers
617  typedef enum {
618  MCP2515_RX_BUFFER0 = 0,
619  MCP2515_RX_BUFFER1 = 1
620  } MCP2515_RX_BUFFER_T;
621 
622  // An enum to specify one of the 6 rx filters
623  typedef enum {
624  MCP2515_RX_FILTER0 = 0,
625  MCP2515_RX_FILTER1 = 1,
626  MCP2515_RX_FILTER2 = 2,
627  MCP2515_RX_FILTER3 = 3,
628  MCP2515_RX_FILTER4 = 4,
629  MCP2515_RX_FILTER5 = 5
630  } MCP2515_RX_FILTER_T;
631 
632  // An enum to specify one of the 2 rx masks
633  typedef enum {
634  MCP2515_RX_MASK0 = 0,
635  MCP2515_RX_MASK1 = 1
636  } MCP2515_RX_MASK_T;
637 
638 
639 #ifdef __cplusplus
640 }
641 #endif
Definition: mcp2515_regs.h:71
Definition: mcp2515_regs.h:59
Definition: mcp2515_regs.h:92