UPM

The UPM API is a high level sensor library for IoT devices using MRAA. See examples here. Back to index page.
SparkFun sensor images provided under CC BY-NC-SA-3.0.

LSM9DS0 Class

Module: lsm9ds0
  • ID: lsm9ds0
  • Name: Triaxial Gyroscope/accelerometer/magnetometer Sensor
  • Category: accelerometer compass
  • Manufacturer: sparkfun stmicro
  • Connection: i2c gpio
  • Link: https://www.sparkfun.com/products/13033

The LSM9DS0 is a system-in-package featuring a 3D digital linear acceleration sensor, a 3D digital angular rate sensor, and a 3D digital magnetic sensor.
The LSM9DS0 has a linear acceleration full scale of 2g/4g/6g/8g/16g, a magnetic field full scale of 2/4/8/12 gauss and an angular rate of 245/500/2000 dps.
While not all of the functionality of this device is supported initially, methods and register definitions are provided that should allow an end user to implement whatever features are required.
This driver was developed on a Sparkfun 9DOF edison block.
lsm9ds0.jpg

Item Index

Methods

Properties

Methods

LSM9DS0

(
  • bus
  • raw
  • gAddress
  • xmAddress
)
Number

lsm9ds0 constructor

Parameters:

  • bus Number

    i2c bus to use

  • raw Boolean

    bypass board definition file, set to true if using Sparkfun 9DOF Block on an Intel Edison Arduino board

  • gAddress Number

    the gyroscope address for this device

  • xmAddress Number

    the accelerometer/magnetometer address for this device

Returns:

Number:

init

() Boolean

set up initial values and start operation

Returns:

Boolean:

true if successful

update

()

update the accelerometer, gyroscope, magnetometer and termperature values.

updateGyroscope

()

update the gyroscope values only

updateAccelerometer

()

update the accelerometer values only

updateMagnetometer

()

update the magnetometer values only

updateTemperature

()

update the temperature value only

readReg

(
  • dev
  • reg
)
Number

read a register

Parameters:

  • dev DEVICE_T

    the device to access (XM or G)

  • reg Number

    the register to read

Returns:

Number:

the value of the register

readRegs

(
  • dev
  • reg
  • buffer
  • len
)

read contiguous register into a buffer

Parameters:

  • dev DEVICE_T

    the device to access (XM or G)

  • reg Number

    the register to start reading at

  • buffer Uint8_t *

    undefined

  • len Number

    the number of registers to read

writeReg

(
  • dev
  • reg
  • val
)
Boolean

write to a register

Parameters:

  • dev DEVICE_T

    the device to access (XM or G)

  • reg Number

    the register to write to

  • val Number

    the value to write

Returns:

Boolean:

true if successful, false otherwise

setGyroscopePowerDown

(
  • enable
)
Boolean

enable or disable the gyro power down mode

Parameters:

  • enable Boolean

    true to put device to sleep, false to wake up

Returns:

Boolean:

true if successful, false otherwise

setGyroscopeEnableAxes

(
  • axes
)
Boolean

enable or disable gyroscope axes. If all axis are disabled, and powerdown mode is not set, then the gyro goes into sleep mode.

Parameters:

  • axes Number

    bit mask of valid axes, (CTRL_REG1_G_YEN, ...)

Returns:

Boolean:

true if successful, false otherwise

setGyroscopeODR

(
  • odr
)
Boolean

set the gyroscope Output Data Rate (ODR)

Parameters:

  • odr G_ODR_T

    one of the G_ODR_T values

Returns:

Boolean:

true if successful, false otherwise

setGyroscopeScale

(
  • scale
)
Boolean

set the scaling mode of the gyroscope

Parameters:

  • scale G_FS_T

    one of the G_FS_T values

Returns:

Boolean:

true if successful, false otherwise

setAccelerometerEnableAxes

(
  • axes
)
Boolean

enable or disable accelerometer axes.

Parameters:

  • axes Number

    bit mask of valid axes, (CTRL_REG1_XM_AXEN, ...)

Returns:

Boolean:

true if successful, false otherwise

setAccelerometerODR

(
  • odr
)
Boolean

set the accelerometer Output Data Rate (ODR)

Parameters:

  • odr XM_AODR_T

    one of the XM_AODR_T values

Returns:

Boolean:

true if successful, false otherwise

setAccelerometerScale

(
  • scale
)
Boolean

set the scaling mode of the accelerometer

Parameters:

  • scale XM_AFS_T

    one of the XM_AFS_T values

Returns:

Boolean:

true if successful, false otherwise

setMagnetometerResolution

(
  • res
)
Boolean

set the magnetometer resolution

Parameters:

  • res XM_RES_T

    one of the XM_RES_T values

Returns:

Boolean:

true if successful, false otherwise

setMagnetometerODR

(
  • odr
)
Boolean

set the magnetometer Output Data Rate (ODR)

Parameters:

  • odr XM_ODR_T

    one of the XM_ODR_T values

Returns:

Boolean:

true if successful, false otherwise

setMagnetometerMode

(
  • mode
)
Boolean

set the magnetometer sensor mode

Parameters:

  • mode XM_MD_T

    one of the XM_MD_T values

Returns:

Boolean:

true if successful, false otherwise

setMagnetometerLPM

(
  • enable
)
Boolean

enable or disable magnetometer low power mode (LPM). When in low power mode, the magnetometer updates at 3.125Hz, regardless of it's ODR setting.

Parameters:

  • enable Boolean

    true to enable LPM, false otherwise

Returns:

Boolean:

true if successful, false otherwise

setMagnetometerScale

(
  • scale
)
Boolean

set the scaling mode of the magnetometer

Parameters:

  • scale XM_MFS_T

    one of the XM_MFS_T values

Returns:

Boolean:

true if successful, false otherwise

getAccelerometer

(
  • x
  • y
  • z
)

get the accelerometer values in gravities

Parameters:

  • x Float *

    the returned x value, if arg is non-NULL

  • y Float *

    the returned y value, if arg is non-NULL

  • z Float *

    the returned z value, if arg is non-NULL

getGyroscope

(
  • x
  • y
  • z
)

get the gyroscope values in degrees per second

Parameters:

  • x Float *

    the returned x value, if arg is non-NULL

  • y Float *

    the returned y value, if arg is non-NULL

  • z Float *

    the returned z value, if arg is non-NULL

getMagnetometer

(
  • x
  • y
  • z
)

get the magnetometer values in gauss

Parameters:

  • x Float *

    the returned x value, if arg is non-NULL

  • y Float *

    the returned y value, if arg is non-NULL

  • z Float *

    the returned z value, if arg is non-NULL

getAccelerometer

() Std::vector float

get the accelerometer values in gravities

Returns:

Std::vector float :

std::vector containing X, Y, Z acceleration values

getGyroscope

() Std::vector float

get the gyroscope values in degrees per second

Returns:

Std::vector float :

std::vector containing X, Y, Z gyroscope values

getMagnetometer

() Std::vector float

get the magnetometer values in gauss

Returns:

Std::vector float :

std::vector containing X, Y, Z magnetometer values

getTemperature

() Number

get the temperature value. Unfortunately the datasheet does not provide a mechanism to convert the temperature value into the correct value, so I made a 'guess'. If it's wrong, and you figure it out, send a patch!

Returns:

Number:

the temperature value in degrees Celsius

enableTemperatureSensor

(
  • enable
)
Boolean

enable onboard temperature measurement sensor

Parameters:

  • enable Boolean

    true to enable temperature sensor, false to disable

Returns:

Boolean:

true if successful, false otherwise

getGyroscopeStatus

() Number

return the gyroscope status register

Returns:

Number:

bitmask of STATUS_REG_G_BITS_T bits

getMagnetometerStatus

() Number

return the magnetometer status register

Returns:

Number:

bitmask of STATUS_REG_M_BITS_T bits

getAccelerometerStatus

() Number

return the accelerometer status register

Returns:

Number:

bitmask of STATUS_REG_A_BITS_T bits

getGyroscopeInterruptConfig

() Number

return the gyroscope interrupt config register

Returns:

Number:

bitmask of INT1_CFG_G_BITS_T bits

setGyroscopeInterruptConfig

(
  • enables
)
Boolean

set the gyroscope interrupt config register

Parameters:

  • enables Number

    bitmask of INT1_CFG_G_BITS_T values

Returns:

Boolean:

true if successful

getGyroscopeInterruptSrc

() Number

return the gyroscope interrupt src register

Returns:

Number:

bitmask of INT1_SRC_G_BITS_T bits

getMagnetometerInterruptControl

() Number

return the magnetometer interrupt control register

Returns:

Number:

bitmask of INT_CTRL_REG_M_BITS_T bits

setMagnetometerInterruptControl

(
  • enables
)
Boolean

set the magnetometer interrupt control register

Parameters:

  • enables Number

    bitmask of INT_CTRL_REG_M_BITS_T values

Returns:

Boolean:

true if successful

getMagnetometerInterruptSrc

() Number

return the magnetometer interrupt src register

Returns:

Number:

bitmask of INT_SRC_REG_M_BITS_T bits

getInterruptGen1

() Number

return the inertial interrupt generator 1 register

Returns:

Number:

bitmask of INT_GEN_X_REG_BITS_T bits

setInterruptGen1

(
  • enables
)
Boolean

set the inertial interrupt generator 1 register

Parameters:

  • enables Number

    bitmask of INT_GEN_X_REG_BITS_T values

Returns:

Boolean:

true if successful

getInterruptGen1Src

() Number

return the inertial interrupt generator 1 src register

Returns:

Number:

bitmask of INT_GEN_X_SRC_BITS_T bits

getInterruptGen2

() Number

return the inertial interrupt generator 2 register

Returns:

Number:

bitmask of INT_GEN_X_REG_BITS_T bits

setInterruptGen2

(
  • enables
)
Boolean

set the inertial interrupt generator 2 register

Parameters:

  • enables Number

    bitmask of INT_GEN_X_REG_BITS_T values

Returns:

Boolean:

true if successful

getInterruptGen2Src

() Number

return the inertial interrupt generator 2 src register

Returns:

Number:

bitmask of INT_GEN_X_SRC_BITS_T bits

installISR

(
  • intr
  • gpio
  • level
  • isr
  • arg
)

install an interrupt handler.

Parameters:

  • intr INTERRUPT_PINS_T

    one of the INTERRUPT_PINS_T values specifying which interrupt pin out of 4 you are installing

  • gpio Number

    gpio pin to use as interrupt pin

  • level Mraa::Edge

    the interrupt trigger level (one of mraa::Edge values). Make sure that you have configured the interrupt pin properly for whatever level you choose.

  • isr Function

    the interrupt handler, accepting a void * argument

  • arg Void *

    the argument to pass the the interrupt handler

uninstallISR

(
  • intr
)

uninstall a previously installed interrupt handler

Parameters:

  • intr INTERRUPT_PINS_T

    one of the INTERRUPT_PINS_T values specifying which interrupt pin out of 4 you are uninstalling

Properties

REG_WHO_AM_I_G

Enum REG_G_T

REG_CTRL_REG1_G

Enum REG_G_T

REG_CTRL_REG2_G

Enum REG_G_T

REG_CTRL_REG3_G

Enum REG_G_T

REG_CTRL_REG4_G

Enum REG_G_T

REG_CTRL_REG5_G

Enum REG_G_T

REG_REFERENCE_G

Enum REG_G_T

REG_STATUS_REG_G

Enum REG_G_T

REG_OUT_X_L_G

Enum REG_G_T

REG_OUT_X_H_G

Enum REG_G_T

REG_OUT_Y_L_G

Enum REG_G_T

REG_OUT_Y_H_G

Enum REG_G_T

REG_OUT_Z_L_G

Enum REG_G_T

REG_OUT_Z_H_G

Enum REG_G_T

REG_FIFO_CTRL_REG_G

Enum REG_G_T

REG_FIFO_SRC_REG_G

Enum REG_G_T

REG_INT1_CFG_G

Enum REG_G_T

REG_INT1_SRC_G

Enum REG_G_T

REG_INT1_TSH_XH_G

Enum REG_G_T

REG_INT1_TSH_XL_G

Enum REG_G_T

REG_INT1_TSH_YH_G

Enum REG_G_T

REG_INT1_TSH_YL_G

Enum REG_G_T

REG_INT1_TSH_ZH_G

Enum REG_G_T

REG_INT1_TSH_ZL_G

Enum REG_G_T

REG_INT1_DURATION_G

Enum REG_G_T

CTRL_REG1_G_YEN

Enum CTRL_REG1_G_BITS_T

CTRL_REG1_G_XEN

Enum CTRL_REG1_G_BITS_T

CTRL_REG1_G_ZEN

Enum CTRL_REG1_G_BITS_T

CTRL_REG1_G_PD

Enum CTRL_REG1_G_BITS_T

CTRL_REG1_G_BW0

Enum CTRL_REG1_G_BITS_T

CTRL_REG1_G_BW1

Enum CTRL_REG1_G_BITS_T

_CTRL_REG1_G_BW_MASK

Enum CTRL_REG1_G_BITS_T

_CTRL_REG1_G_BW_SHIFT

Enum CTRL_REG1_G_BITS_T

CTRL_REG1_G_DR0

Enum CTRL_REG1_G_BITS_T

CTRL_REG1_G_DR1

Enum CTRL_REG1_G_BITS_T

_CTRL_REG1_G_DR_MASK

Enum CTRL_REG1_G_BITS_T

_CTRL_REG1_G_DR_SHIFT

Enum CTRL_REG1_G_BITS_T

CTRL_REG1_G_ODR0

Enum CTRL_REG1_G_BITS_T

CTRL_REG1_G_ODR1

Enum CTRL_REG1_G_BITS_T

CTRL_REG1_G_ODR2

Enum CTRL_REG1_G_BITS_T

CTRL_REG1_G_ODR3

Enum CTRL_REG1_G_BITS_T

_CTRL_REG1_G_ODR_MASK

Enum CTRL_REG1_G_BITS_T

_CTRL_REG1_G_ODR_SHIFT

Enum CTRL_REG1_G_BITS_T

G_ODR_95_12_5

Enum G_ODR_T

G_ODR_95_25

Enum G_ODR_T

G_ODR_190_12_5

Enum G_ODR_T

G_ODR_190_25

Enum G_ODR_T

G_ODR_190_50

Enum G_ODR_T

G_ODR_190_70

Enum G_ODR_T

G_ODR_380_20

Enum G_ODR_T

G_ODR_380_25

Enum G_ODR_T

G_ODR_380_50

Enum G_ODR_T

G_ODR_380_100

Enum G_ODR_T

G_ODR_760_30

Enum G_ODR_T

G_ODR_760_35

Enum G_ODR_T

G_ODR_760_50

Enum G_ODR_T

G_ODR_760_100

Enum G_ODR_T

CTRL_REG2_G_HPCF0

Enum CTRL_REG2_G_BITS_T

CTRL_REG2_G_HPCF1

Enum CTRL_REG2_G_BITS_T

CTRL_REG2_G_HPCF2

Enum CTRL_REG2_G_BITS_T

CTRL_REG2_G_HPCF3

Enum CTRL_REG2_G_BITS_T

_CTRL_REG2_G_HPCF_MASK

Enum CTRL_REG2_G_BITS_T

_CTRL_REG2_G_HPCF_SHIFT

Enum CTRL_REG2_G_BITS_T

CTRL_REG2_G_HPM0

Enum CTRL_REG2_G_BITS_T

CTRL_REG2_G_HPM1

Enum CTRL_REG2_G_BITS_T

_CTRL_REG2_G_HPM_MASK

Enum CTRL_REG2_G_BITS_T

_CTRL_REG2_G_HPM_SHIFT

Enum CTRL_REG2_G_BITS_T

G_HPCF_7_2

Enum G_HPCF_T

G_HPCF_3_5

Enum G_HPCF_T

G_HPCF_1_8

Enum G_HPCF_T

G_HPCF_0_9

Enum G_HPCF_T

G_HPCF_0_45

Enum G_HPCF_T

G_HPCF_0_18

Enum G_HPCF_T

G_HPCF_0_09

Enum G_HPCF_T

G_HPCF_0_045

Enum G_HPCF_T

G_HPCF_0_018

Enum G_HPCF_T

G_HPCF_0_009

Enum G_HPCF_T

G_HPM_NORMAL_RESET_HPF

Enum G_HPM_T

G_HPM_REFERENCE

Enum G_HPM_T

G_HPM_NORMAL

Enum G_HPM_T

G_HPM_AUTORESET_ON_INTR

Enum G_HPM_T

CTRL_REG3_G_I2_EMPTY

Enum CTRL_REG3_G_BITS_T

CTRL_REG3_G_I2_ORUN

Enum CTRL_REG3_G_BITS_T

CTRL_REG3_G_I2_WTM

Enum CTRL_REG3_G_BITS_T

CTRL_REG3_G_I2_DRDY

Enum CTRL_REG3_G_BITS_T

CTRL_REG3_G_PP_OD

Enum CTRL_REG3_G_BITS_T

CTRL_REG3_G_H_LACTIVE

Enum CTRL_REG3_G_BITS_T

CTRL_REG3_G_I1_BOOT

Enum CTRL_REG3_G_BITS_T

CTRL_REG3_G_I1_INT1

Enum CTRL_REG3_G_BITS_T

CTRL_REG4_G_SIM

Enum CTRL_REG4_G_BITS_T

CTRL_REG4_G_ST0

Enum CTRL_REG4_G_BITS_T

CTRL_REG4_G_ST1

Enum CTRL_REG4_G_BITS_T

_CTRL_REG4_G_ST_MASK

Enum CTRL_REG4_G_BITS_T

_CTRL_REG4_G_ST_SHIFT

Enum CTRL_REG4_G_BITS_T

CTRL_REG4_G_FS0

Enum CTRL_REG4_G_BITS_T

CTRL_REG4_G_FS1

Enum CTRL_REG4_G_BITS_T

_CTRL_REG4_G_FS_MASK

Enum CTRL_REG4_G_BITS_T

_CTRL_REG4_G_FS_SHIFT

Enum CTRL_REG4_G_BITS_T

CTRL_REG4_G_BLE

Enum CTRL_REG4_G_BITS_T

CTRL_REG4_G_BDU

Enum CTRL_REG4_G_BITS_T

G_ST_NORMAL

Enum G_ST_T

G_ST_SELFTEST0

Enum G_ST_T

G_ST_SELFTEST1

Enum G_ST_T

G_FS_245

Enum G_FS_T

G_FS_500

Enum G_FS_T

G_FS_2000

Enum G_FS_T

CTRL_REG5_G_OUTSEL0

Enum CTRL_REG5_G_BITS_T

CTRL_REG5_G_OUTSEL1

Enum CTRL_REG5_G_BITS_T

_CTRL_REG5_G_OUTSEL_MASK

Enum CTRL_REG5_G_BITS_T

_CTRL_REG5_G_OUTSEL_SHIFT

Enum CTRL_REG5_G_BITS_T

CTRL_REG5_G_INT1SEL0

Enum CTRL_REG5_G_BITS_T

CTRL_REG5_G_INT1SEL1

Enum CTRL_REG5_G_BITS_T

_CTRL_REG5_G_INT1SEL_MASK

Enum CTRL_REG5_G_BITS_T

_CTRL_REG5_G_INT1SEL_SHIFT

Enum CTRL_REG5_G_BITS_T

CTRL_REG5_G_HPEN

Enum CTRL_REG5_G_BITS_T

CTRL_REG5_G_FIFO_EN

Enum CTRL_REG5_G_BITS_T

CTRL_REG5_G_BOOT

Enum CTRL_REG5_G_BITS_T

G_INT1OUTSEL_0

Enum G_INT1OUTSEL_T

G_INT1OUTSEL_1

Enum G_INT1OUTSEL_T

G_INT1OUTSEL_2

Enum G_INT1OUTSEL_T

G_INT1OUTSEL_3

Enum G_INT1OUTSEL_T

STATUS_REG_G_XDA

Enum STATUS_REG_G_BITS_T

STATUS_REG_G_YDA

Enum STATUS_REG_G_BITS_T

STATUS_REG_G_ZDA

Enum STATUS_REG_G_BITS_T

STATUS_REG_G_ZYXDA

Enum STATUS_REG_G_BITS_T

STATUS_REG_G_XOR

Enum STATUS_REG_G_BITS_T

STATUS_REG_G_YOR

Enum STATUS_REG_G_BITS_T

STATUS_REG_G_ZOR

Enum STATUS_REG_G_BITS_T

STATUS_REG_G_ZYXOR

Enum STATUS_REG_G_BITS_T

FIFO_CTRL_REG_G_WTM0

Enum FIFO_CTRL_REG_G_T

FIFO_CTRL_REG_G_WTM1

Enum FIFO_CTRL_REG_G_T

FIFO_CTRL_REG_G_WTM2

Enum FIFO_CTRL_REG_G_T

FIFO_CTRL_REG_G_WTM3

Enum FIFO_CTRL_REG_G_T

FIFO_CTRL_REG_G_WTM4

Enum FIFO_CTRL_REG_G_T

_FIFO_CTRL_REG_G_WTM_MASK

Enum FIFO_CTRL_REG_G_T

_FIFO_CTRL_REG_G_WTM_SHIFT

Enum FIFO_CTRL_REG_G_T

FIFO_CTRL_REG_G_FM0

Enum FIFO_CTRL_REG_G_T

FIFO_CTRL_REG_G_FM1

Enum FIFO_CTRL_REG_G_T

FIFO_CTRL_REG_G_FM2

Enum FIFO_CTRL_REG_G_T

_FIFO_CTRL_REG_G_FM_MASK

Enum FIFO_CTRL_REG_G_T

_FIFO_CTRL_REG_G_FM_SHIFT

Enum FIFO_CTRL_REG_G_T

G_FM_BYPASS

Enum G_FM_T

G_FM_FIFO

Enum G_FM_T

G_FM_STREAM

Enum G_FM_T

G_FM_STREAM2FIFO

Enum G_FM_T

G_FM_BYPASS2STREAM

Enum G_FM_T

FIFO_CTRL_REG_G_FSS0

Enum FIFO_SRC_REG_G_BITS_T

FIFO_CTRL_REG_G_FSS1

Enum FIFO_SRC_REG_G_BITS_T

FIFO_CTRL_REG_G_FSS2

Enum FIFO_SRC_REG_G_BITS_T

FIFO_CTRL_REG_G_FSS3

Enum FIFO_SRC_REG_G_BITS_T

FIFO_CTRL_REG_G_FSS4

Enum FIFO_SRC_REG_G_BITS_T

_FIFO_CTRL_REG_G_FSS_MASK

Enum FIFO_SRC_REG_G_BITS_T

_FIFO_CTRL_REG_G_FSS_SHIFT

Enum FIFO_SRC_REG_G_BITS_T

FIFO_CTRL_REG_G_EMPTY

Enum FIFO_SRC_REG_G_BITS_T

FIFO_CTRL_REG_G_OVRN

Enum FIFO_SRC_REG_G_BITS_T

FIFO_CTRL_REG_G_WTM

Enum FIFO_SRC_REG_G_BITS_T

INT1_CFG_G_XLIE

Enum INT1_CFG_G_BITS_T

INT1_CFG_G_XHIE

Enum INT1_CFG_G_BITS_T

INT1_CFG_G_YLIE

Enum INT1_CFG_G_BITS_T

INT1_CFG_G_YHIE

Enum INT1_CFG_G_BITS_T

INT1_CFG_G_ZLIE

Enum INT1_CFG_G_BITS_T

INT1_CFG_G_ZHIE

Enum INT1_CFG_G_BITS_T

INT1_CFG_G_LIR

Enum INT1_CFG_G_BITS_T

INT1_CFG_G_ANDOR

Enum INT1_CFG_G_BITS_T

INT1_SRC_G_XL

Enum INT1_SRC_G_BITS_T

INT1_SRC_G_XH

Enum INT1_SRC_G_BITS_T

INT1_SRC_G_YL

Enum INT1_SRC_G_BITS_T

INT1_SRC_G_YH

Enum INT1_SRC_G_BITS_T

INT1_SRC_G_ZL

Enum INT1_SRC_G_BITS_T

INT1_SRC_G_ZH

Enum INT1_SRC_G_BITS_T

INT1_SRC_G_IA

Enum INT1_SRC_G_BITS_T

REG_OUT_TEMP_L_XM

Enum REG_XM_T

REG_OUT_TEMP_H_XM

Enum REG_XM_T

REG_STATUS_REG_M

Enum REG_XM_T

REG_OUT_X_L_M

Enum REG_XM_T

REG_OUT_X_H_M

Enum REG_XM_T

REG_OUT_Y_L_M

Enum REG_XM_T

REG_OUT_Y_H_M

Enum REG_XM_T

REG_OUT_Z_L_M

Enum REG_XM_T

REG_OUT_Z_H_M

Enum REG_XM_T

REG_WHO_AM_I_XM

Enum REG_XM_T

REG_INT_CTRL_REG_M

Enum REG_XM_T

REG_INT_SRC_REG_M

Enum REG_XM_T

REG_INT_THS_L_M

Enum REG_XM_T

REG_INT_THS_H_M

Enum REG_XM_T

REG_OFFSET_X_L_M

Enum REG_XM_T

REG_OFFSET_X_H_M

Enum REG_XM_T

REG_OFFSET_Y_L_M

Enum REG_XM_T

REG_OFFSET_Y_H_M

Enum REG_XM_T

REG_OFFSET_Z_L_M

Enum REG_XM_T

REG_OFFSET_Z_H_M

Enum REG_XM_T

REG_REFERENCE_X

Enum REG_XM_T

REG_REFERENCE_Y

Enum REG_XM_T

REG_REFERENCE_Z

Enum REG_XM_T

REG_CTRL_REG0_XM

Enum REG_XM_T

REG_CTRL_REG1_XM

Enum REG_XM_T

REG_CTRL_REG2_XM

Enum REG_XM_T

REG_CTRL_REG3_XM

Enum REG_XM_T

REG_CTRL_REG4_XM

Enum REG_XM_T

REG_CTRL_REG5_XM

Enum REG_XM_T

REG_CTRL_REG6_XM

Enum REG_XM_T

REG_CTRL_REG7_XM

Enum REG_XM_T

REG_STATUS_REG_A

Enum REG_XM_T

REG_OUT_X_L_A

Enum REG_XM_T

REG_OUT_X_H_A

Enum REG_XM_T

REG_OUT_Y_L_A

Enum REG_XM_T

REG_OUT_Y_H_A

Enum REG_XM_T

REG_OUT_Z_L_A

Enum REG_XM_T

REG_OUT_Z_H_A

Enum REG_XM_T

REG_FIFO_CTRL_REG

Enum REG_XM_T

REG_FIFO_SRC_REG

Enum REG_XM_T

REG_INT_GEN_1_REG

Enum REG_XM_T

REG_INT_GEN_1_SRC

Enum REG_XM_T

REG_INT_GEN_1_THS

Enum REG_XM_T

REG_INT_GEN_1_DURATION

Enum REG_XM_T

REG_INT_GEN_2_REG

Enum REG_XM_T

REG_INT_GEN_2_SRC

Enum REG_XM_T

REG_INT_GEN_2_THS

Enum REG_XM_T

REG_INT_GEN_2_DURATION

Enum REG_XM_T

REG_CLICK_CFG

Enum REG_XM_T

REG_CLICK_SRC

Enum REG_XM_T

REG_CLICK_THS

Enum REG_XM_T

REG_TIME_LIMIT

Enum REG_XM_T

REG_TIME_LATENCY

Enum REG_XM_T

REG_TIME_WINDOW

Enum REG_XM_T

REG_ACT_THS

Enum REG_XM_T

REG_ACT_DUR

Enum REG_XM_T

STATUS_REG_M_XMDA

Enum STATUS_REG_M_BITS_T

STATUS_REG_M_YMDA

Enum STATUS_REG_M_BITS_T

STATUS_REG_M_ZMDA

Enum STATUS_REG_M_BITS_T

STATUS_REG_M_ZYXMDA

Enum STATUS_REG_M_BITS_T

STATUS_REG_M_XMOR

Enum STATUS_REG_M_BITS_T

STATUS_REG_M_YMOR

Enum STATUS_REG_M_BITS_T

STATUS_REG_M_ZMOR

Enum STATUS_REG_M_BITS_T

STATUS_REG_M_ZYXMOR

Enum STATUS_REG_M_BITS_T

INT_CTRL_REG_M_MIEN

Enum INT_CTRL_REG_M_BITS_T

INT_CTRL_REG_M_4D

Enum INT_CTRL_REG_M_BITS_T

INT_CTRL_REG_M_IEL

Enum INT_CTRL_REG_M_BITS_T

INT_CTRL_REG_M_IEA

Enum INT_CTRL_REG_M_BITS_T

INT_CTRL_REG_M_PP_OD

Enum INT_CTRL_REG_M_BITS_T

INT_CTRL_REG_M_ZMIEN

Enum INT_CTRL_REG_M_BITS_T

INT_CTRL_REG_M_YMIEN

Enum INT_CTRL_REG_M_BITS_T

INT_CTRL_REG_M_XMIEN

Enum INT_CTRL_REG_M_BITS_T

INT_SRC_REG_M_MINT

Enum INT_SRC_REG_M_BITS_T

INT_SRC_REG_M_MROI

Enum INT_SRC_REG_M_BITS_T

INT_SRC_REG_M_NTH_Z

Enum INT_SRC_REG_M_BITS_T

INT_SRC_REG_M_NTH_Y

Enum INT_SRC_REG_M_BITS_T

INT_SRC_REG_M_NTH_X

Enum INT_SRC_REG_M_BITS_T

INT_SRC_REG_M_PTH_Z

Enum INT_SRC_REG_M_BITS_T

INT_SRC_REG_M_PTH_Y

Enum INT_SRC_REG_M_BITS_T

INT_SRC_REG_M_PTH_X

Enum INT_SRC_REG_M_BITS_T

CTRL_REG0_XM_HPIS2

Enum CTRL_REG0_XM_BITS_T

CTRL_REG0_XM_HPIS1

Enum CTRL_REG0_XM_BITS_T

CTRL_REG0_XM_HP_CLICK

Enum CTRL_REG0_XM_BITS_T

CTRL_REG0_XM_WTM_LEN

Enum CTRL_REG0_XM_BITS_T

CTRL_REG0_XM_FIFO_EN

Enum CTRL_REG0_XM_BITS_T

CTRL_REG0_XM_BOOT

Enum CTRL_REG0_XM_BITS_T

CTRL_REG1_XM_AXEN

Enum CTRL_REG1_XM_BITS_T

CTRL_REG1_XM_AYEN

Enum CTRL_REG1_XM_BITS_T

CTRL_REG1_XM_AZEN

Enum CTRL_REG1_XM_BITS_T

CTRL_REG1_XM_BDU

Enum CTRL_REG1_XM_BITS_T

CTRL_REG1_XM_AODR0

Enum CTRL_REG1_XM_BITS_T

CTRL_REG1_XM_AODR1

Enum CTRL_REG1_XM_BITS_T

CTRL_REG1_XM_AODR2

Enum CTRL_REG1_XM_BITS_T

CTRL_REG1_XM_AODR3

Enum CTRL_REG1_XM_BITS_T

_CTRL_REG1_XM_AODR_MASK

Enum CTRL_REG1_XM_BITS_T

_CTRL_REG1_XM_AODR_SHIFT

Enum CTRL_REG1_XM_BITS_T

XM_AODR_PWRDWN

Enum XM_AODR_T

XM_AODR_3_125

Enum XM_AODR_T

XM_AODR_6_25

Enum XM_AODR_T

XM_AODR_12_5

Enum XM_AODR_T

XM_AODR_25

Enum XM_AODR_T

XM_AODR_50

Enum XM_AODR_T

XM_AODR_100

Enum XM_AODR_T

XM_AODR_200

Enum XM_AODR_T

XM_AODR_400

Enum XM_AODR_T

XM_AODR_800

Enum XM_AODR_T

XM_AODR_1000

Enum XM_AODR_T

CTRL_REG2_XM_SIM

Enum CTRL_REG2_XM_BITS_T

CTRL_REG2_XM_AST0

Enum CTRL_REG2_XM_BITS_T

CTRL_REG2_XM_AST1

Enum CTRL_REG2_XM_BITS_T

_CTRL_REG2_XM_AST_MASK

Enum CTRL_REG2_XM_BITS_T

_CTRL_REG2_XM_AST_SHIFT

Enum CTRL_REG2_XM_BITS_T

CTRL_REG2_XM_AFS0

Enum CTRL_REG2_XM_BITS_T

CTRL_REG2_XM_AFS1

Enum CTRL_REG2_XM_BITS_T

CTRL_REG2_XM_AFS2

Enum CTRL_REG2_XM_BITS_T

_CTRL_REG2_XM_AFS_MASK

Enum CTRL_REG2_XM_BITS_T

_CTRL_REG2_XM_AFS_SHIFT

Enum CTRL_REG2_XM_BITS_T

CTRL_REG2_XM_ABW0

Enum CTRL_REG2_XM_BITS_T

CTRL_REG2_XM_ABW1

Enum CTRL_REG2_XM_BITS_T

_CTRL_REG2_XM_ABW_MASK

Enum CTRL_REG2_XM_BITS_T

_CTRL_REG2_XM_ABW_SHIFT

Enum CTRL_REG2_XM_BITS_T

XM_AST_NORMAL

Enum XM_AST_T

XM_AST_POS_SIGN

Enum XM_AST_T

XM_AST_NEG_SIGN

Enum XM_AST_T

XM_AFS_2

Enum XM_AFS_T

XM_AFS_4

Enum XM_AFS_T

XM_AFS_6

Enum XM_AFS_T

XM_AFS_8

Enum XM_AFS_T

XM_AFS_16

Enum XM_AFS_T

XM_ABW_773

Enum XM_ABW_T

XM_ABW_194

Enum XM_ABW_T

XM_ABW_362

Enum XM_ABW_T

XM_ABW_50

Enum XM_ABW_T

CTRL_REG3_XM_P1_EMPTY

Enum CTRL_REG3_XM_BITS_T

CTRL_REG3_XM_P1_DRDYM

Enum CTRL_REG3_XM_BITS_T

CTRL_REG3_XM_P1_DRDYA

Enum CTRL_REG3_XM_BITS_T

CTRL_REG3_XM_P1_INTM

Enum CTRL_REG3_XM_BITS_T

CTRL_REG3_XM_P1_INT2

Enum CTRL_REG3_XM_BITS_T

CTRL_REG3_XM_P1_INT1

Enum CTRL_REG3_XM_BITS_T

CTRL_REG3_XM_P1_TAP

Enum CTRL_REG3_XM_BITS_T

CTRL_REG3_XM_P1_BOOT

Enum CTRL_REG3_XM_BITS_T

CTRL_REG4_XM_P2_WTM

Enum CTRL_REG4_XM_BITS_T

CTRL_REG4_XM_P2_OVERRUN

Enum CTRL_REG4_XM_BITS_T

CTRL_REG4_XM_P2_DRDYM

Enum CTRL_REG4_XM_BITS_T

CTRL_REG4_XM_P2_DRDYA

Enum CTRL_REG4_XM_BITS_T

CTRL_REG4_XM_P2_INTM

Enum CTRL_REG4_XM_BITS_T

CTRL_REG4_XM_P2_INT2

Enum CTRL_REG4_XM_BITS_T

CTRL_REG4_XM_P2_INT1

Enum CTRL_REG4_XM_BITS_T

CTRL_REG4_XM_P2_TAP

Enum CTRL_REG4_XM_BITS_T

CTRL_REG5_XM_LIR1

Enum CTRL_REG5_XM_BITS_T

CTRL_REG5_XM_LIR2

Enum CTRL_REG5_XM_BITS_T

CTRL_REG5_XM_ODR0

Enum CTRL_REG5_XM_BITS_T

CTRL_REG5_XM_ODR1

Enum CTRL_REG5_XM_BITS_T

CTRL_REG5_XM_ODR2

Enum CTRL_REG5_XM_BITS_T

_CTRL_REG5_XM_ODR_MASK

Enum CTRL_REG5_XM_BITS_T

_CTRL_REG5_XM_ODR_SHIFT

Enum CTRL_REG5_XM_BITS_T

CTRL_REG5_XM_RES0

Enum CTRL_REG5_XM_BITS_T

CTRL_REG5_XM_RES1

Enum CTRL_REG5_XM_BITS_T

_CTRL_REG5_XM_RES_MASK

Enum CTRL_REG5_XM_BITS_T

_CTRL_REG5_XM_RES_SHIFT

Enum CTRL_REG5_XM_BITS_T

CTRL_REG5_XM_TEMP_EN

Enum CTRL_REG5_XM_BITS_T

XM_ODR_3_125

Enum XM_ODR_T

XM_ODR_6_25

Enum XM_ODR_T

XM_ODR_12_5

Enum XM_ODR_T

XM_ODR_25

Enum XM_ODR_T

XM_ODR_50

Enum XM_ODR_T

XM_ODR_100

Enum XM_ODR_T

XM_RES_LOW

Enum XM_RES_T

XM_RES_HIGH

Enum XM_RES_T

CTRL_REG6_XM_MFS0

Enum CTRL_REG6_XM_BITS_T

CTRL_REG6_XM_MFS1

Enum CTRL_REG6_XM_BITS_T

_CTRL_REG6_XM_MFS_MASK

Enum CTRL_REG6_XM_BITS_T

_CTRL_REG6_XM_MFS_SHIFT

Enum CTRL_REG6_XM_BITS_T

XM_MFS_2

Enum XM_MFS_T

XM_MFS_4

Enum XM_MFS_T

XM_MFS_8

Enum XM_MFS_T

XM_MFS_12

Enum XM_MFS_T

CTRL_REG7_XM_MD0

Enum CTRL_REG7_XM_BITS_T

CTRL_REG7_XM_MD1

Enum CTRL_REG7_XM_BITS_T

_CTRL_REG7_XM_MD_MASK

Enum CTRL_REG7_XM_BITS_T

_CTRL_REG7_XM_MD_SHIFT

Enum CTRL_REG7_XM_BITS_T

CTRL_REG7_XM_MLP

Enum CTRL_REG7_XM_BITS_T

CTRL_REG7_XM_AFDS

Enum CTRL_REG7_XM_BITS_T

CTRL_REG7_XM_AHPM0

Enum CTRL_REG7_XM_BITS_T

CTRL_REG7_XM_AHPM1

Enum CTRL_REG7_XM_BITS_T

_CTRL_REG7_XM_AHPM_MASK

Enum CTRL_REG7_XM_BITS_T

_CTRL_REG7_XM_AHPM_SHIFT

Enum CTRL_REG7_XM_BITS_T

XM_MD_CONTINUOUS

Enum XM_MD_T

XM_MD_SINGLE

Enum XM_MD_T

XM_MD_POWERDOWN

Enum XM_MD_T

XM_AHPM_NORMAL_REF

Enum XM_AHPM_T

XM_AHPM_REFERENCE

Enum XM_AHPM_T

XM_AHPM_NORMAL

Enum XM_AHPM_T

XM_AHPM_AUTORESET

Enum XM_AHPM_T

STATUS_REG_A_XADA

Enum STATUS_REG_A_BITS_T

STATUS_REG_A_YADA

Enum STATUS_REG_A_BITS_T

STATUS_REG_A_ZADA

Enum STATUS_REG_A_BITS_T

STATUS_REG_A_ZYXADA

Enum STATUS_REG_A_BITS_T

STATUS_REG_A_XAOR

Enum STATUS_REG_A_BITS_T

STATUS_REG_A_YAOR

Enum STATUS_REG_A_BITS_T

STATUS_REG_A_ZAOR

Enum STATUS_REG_A_BITS_T

STATUS_REG_A_ZYXAOR

Enum STATUS_REG_A_BITS_T

FIFO_CTRL_REG_FTH0

Enum FIFO_CTRL_REG_T

FIFO_CTRL_REG_FTH1

Enum FIFO_CTRL_REG_T

FIFO_CTRL_REG_FTH2

Enum FIFO_CTRL_REG_T

FIFO_CTRL_REG_FTH3

Enum FIFO_CTRL_REG_T

FIFO_CTRL_REG_FTH4

Enum FIFO_CTRL_REG_T

_FIFO_CTRL_REG_FTH_MASK

Enum FIFO_CTRL_REG_T

_FIFO_CTRL_REG_FTH_SHIFT

Enum FIFO_CTRL_REG_T

FIFO_CTRL_REG_FM0

Enum FIFO_CTRL_REG_T

FIFO_CTRL_REG_FM1

Enum FIFO_CTRL_REG_T

FIFO_CTRL_REG_FM2

Enum FIFO_CTRL_REG_T

_FIFO_CTRL_REG_FM_MASK

Enum FIFO_CTRL_REG_T

_FIFO_CTRL_REG_FM_SHIFT

Enum FIFO_CTRL_REG_T

FM_BYPASS

Enum FM_T

FM_FIFO

Enum FM_T

FM_STREAM

Enum FM_T

FM_STREAM2FIFO

Enum FM_T

FM_BYPASS2STREAM

Enum FM_T

FIFO_CTRL_REG_FSS0

Enum FIFO_SRC_REG_BITS_T

FIFO_CTRL_REG_FSS1

Enum FIFO_SRC_REG_BITS_T

FIFO_CTRL_REG_FSS2

Enum FIFO_SRC_REG_BITS_T

FIFO_CTRL_REG_FSS3

Enum FIFO_SRC_REG_BITS_T

FIFO_CTRL_REG_FSS4

Enum FIFO_SRC_REG_BITS_T

_FIFO_CTRL_REG_FSS_MASK

Enum FIFO_SRC_REG_BITS_T

_FIFO_CTRL_REG_FSS_SHIFT

Enum FIFO_SRC_REG_BITS_T

FIFO_CTRL_REG_EMPTY

Enum FIFO_SRC_REG_BITS_T

FIFO_CTRL_REG_OVRN

Enum FIFO_SRC_REG_BITS_T

FIFO_CTRL_REG_WTM

Enum FIFO_SRC_REG_BITS_T

INT_GEN_X_REG_XLIE_XDOWNE

Enum INT_GEN_X_REG_BITS_T

INT_GEN_X_REG_XHIE_XUPE

Enum INT_GEN_X_REG_BITS_T

INT_GEN_X_REG_YLIE_YDOWNE

Enum INT_GEN_X_REG_BITS_T

INT_GEN_X_REG_YHIE_YUPE

Enum INT_GEN_X_REG_BITS_T

INT_GEN_X_REG_ZLIE_ZDOWNE

Enum INT_GEN_X_REG_BITS_T

INT_GEN_X_REG_ZHIE_ZUPE

Enum INT_GEN_X_REG_BITS_T

INT_GEN_X_REG_6D

Enum INT_GEN_X_REG_BITS_T

INT_GEN_X_REG_AOI

Enum INT_GEN_X_REG_BITS_T

INT_GEN_X_SRC_XL

Enum INT_GEN_X_SRC_BITS_T

INT_GEN_X_SRC_XH

Enum INT_GEN_X_SRC_BITS_T

INT_GEN_X_SRC_YL

Enum INT_GEN_X_SRC_BITS_T

INT_GEN_X_SRC_YH

Enum INT_GEN_X_SRC_BITS_T

INT_GEN_X_SRC_ZL

Enum INT_GEN_X_SRC_BITS_T

INT_GEN_X_SRC_ZH

Enum INT_GEN_X_SRC_BITS_T

INT_GEN_X_SRC_IA

Enum INT_GEN_X_SRC_BITS_T

INT_GEN_X_THS0

Enum INT_GEN_X_THS_BITS_T

INT_GEN_X_THS1

Enum INT_GEN_X_THS_BITS_T

INT_GEN_X_THS2

Enum INT_GEN_X_THS_BITS_T

INT_GEN_X_THS3

Enum INT_GEN_X_THS_BITS_T

INT_GEN_X_THS4

Enum INT_GEN_X_THS_BITS_T

INT_GEN_X_THS5

Enum INT_GEN_X_THS_BITS_T

INT_GEN_X_THS6

Enum INT_GEN_X_THS_BITS_T

_INT_GEN_X_THS_MASK

Enum INT_GEN_X_THS_BITS_T

_INT_GEN_X_THS_SHIFT

Enum INT_GEN_X_THS_BITS_T

INT_GEN_X_DUR0

Enum INT_GEN_X_DUR_BITS_T

INT_GEN_X_DUR1

Enum INT_GEN_X_DUR_BITS_T

INT_GEN_X_DUR2

Enum INT_GEN_X_DUR_BITS_T

INT_GEN_X_DUR3

Enum INT_GEN_X_DUR_BITS_T

INT_GEN_X_DUR4

Enum INT_GEN_X_DUR_BITS_T

INT_GEN_X_DUR5

Enum INT_GEN_X_DUR_BITS_T

INT_GEN_X_DUR6

Enum INT_GEN_X_DUR_BITS_T

_INT_GEN_X_DUR_MASK

Enum INT_GEN_X_DUR_BITS_T

_INT_GEN_X_DUR_SHIFT

Enum INT_GEN_X_DUR_BITS_T

CLICK_CONFIG_XS

Enum CLICK_CONFIG_BITS_T

CLICK_CONFIG_XD

Enum CLICK_CONFIG_BITS_T

CLICK_CONFIG_YS

Enum CLICK_CONFIG_BITS_T

CLICK_CONFIG_YD

Enum CLICK_CONFIG_BITS_T

CLICK_CONFIG_ZS

Enum CLICK_CONFIG_BITS_T

CLICK_CONFIG_ZD

Enum CLICK_CONFIG_BITS_T

CLICK_SRC_X

Enum CLICK_SRC_BITS_T

CLICK_SRC_Y

Enum CLICK_SRC_BITS_T

CLICK_SRC_Z

Enum CLICK_SRC_BITS_T

CLICK_SRC_SIGN

Enum CLICK_SRC_BITS_T

CLICK_SRC_SCLICK

Enum CLICK_SRC_BITS_T

CLICK_SRC_DCLICK

Enum CLICK_SRC_BITS_T

CLICK_SRC_IA

Enum CLICK_SRC_BITS_T

CLICK_THS_THS0

Enum CLICK_THS_BITS_T

CLICK_THS_THS1

Enum CLICK_THS_BITS_T

CLICK_THS_THS2

Enum CLICK_THS_BITS_T

CLICK_THS_THS3

Enum CLICK_THS_BITS_T

CLICK_THS_THS4

Enum CLICK_THS_BITS_T

CLICK_THS_THS5

Enum CLICK_THS_BITS_T

CLICK_THS_THS6

Enum CLICK_THS_BITS_T

_CLICK_THS_THS_MASK

Enum CLICK_THS_BITS_T

_CLICK_THS_THS_SHIFT

Enum CLICK_THS_BITS_T

CLICK_TIME_LIMIT_TLI0

Enum CLICK_TIME_LIMIT_BITS_T

CLICK_TIME_LIMIT_TLI1

Enum CLICK_TIME_LIMIT_BITS_T

CLICK_TIME_LIMIT_TLI2

Enum CLICK_TIME_LIMIT_BITS_T

CLICK_TIME_LIMIT_TLI3

Enum CLICK_TIME_LIMIT_BITS_T

CLICK_TIME_LIMIT_TLI4

Enum CLICK_TIME_LIMIT_BITS_T

CLICK_TIME_LIMIT_TLI5

Enum CLICK_TIME_LIMIT_BITS_T

CLICK_TIME_LIMIT_TLI6

Enum CLICK_TIME_LIMIT_BITS_T

_CLICK_TIME_LIMIT_TLI_MASK

Enum CLICK_TIME_LIMIT_BITS_T

_CLICK_TIME_LIMIT_TLI_SHIFT

Enum CLICK_TIME_LIMIT_BITS_T

ACT_THS_ACTH0

Enum ACT_THS_BITS_T

ACT_THS_ACTH1

Enum ACT_THS_BITS_T

ACT_THS_ACTH2

Enum ACT_THS_BITS_T

ACT_THS_ACTH3

Enum ACT_THS_BITS_T

ACT_THS_ACTH4

Enum ACT_THS_BITS_T

ACT_THS_ACTH5

Enum ACT_THS_BITS_T

ACT_THS_ACTH6

Enum ACT_THS_BITS_T

_ACT_THS_ACTH_MASK

Enum ACT_THS_BITS_T

_ACT_THS_ACTH_SHIFT

Enum ACT_THS_BITS_T

DEV_GYRO

Enum DEVICE_T

DEV_XM

Enum DEVICE_T

INTERRUPT_G_INT

Enum INTERRUPT_PINS_T

INTERRUPT_G_DRDY

Enum INTERRUPT_PINS_T

INTERRUPT_XM_GEN1

Enum INTERRUPT_PINS_T

INTERRUPT_XM_GEN2

Enum INTERRUPT_PINS_T