upm  1.1.0
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bma250e.hpp
1 /*
2  * Author: Jon Trulson <jtrulson@ics.com>
3  * Copyright (c) 2016 Intel Corporation.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
20  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 #pragma once
25 
26 #include <string>
27 #include <mraa/i2c.hpp>
28 #include <mraa/spi.hpp>
29 #include <mraa/gpio.hpp>
30 
31 #define BMA250E_I2C_BUS 0
32 #define BMA250E_SPI_BUS 0
33 #define BMA250E_DEFAULT_ADDR 0x18
34 
35 
36 namespace upm {
37 
72  class BMA250E {
73  public:
74  // special reset byte
75  static const uint8_t BMA250E_RESET_BYTE = 0xb6;
76 
77  // NOTE: Reserved registers must not be written into. Reading
78  // from them may return indeterminate values. Registers
79  // containing reserved bitfields must be written as 0. Reading
80  // reserved bitfields may return indeterminate values.
81 
85  typedef enum : uint8_t {
86  REG_CHIP_ID = 0x00,
87 
88  // 0x01 reserved
89 
90  REG_ACCD_X_LSB = 0x02,
91  REG_ACCD_X_MSB = 0x03,
92  REG_ACCD_Y_LSB = 0x04,
93  REG_ACCD_Y_MSB = 0x05,
94  REG_ACCD_Z_LSB = 0x06,
95  REG_ACCD_Z_MSB = 0x07,
96 
97  REG_TEMP = 0x08,
98 
99  REG_INT_STATUS_0 = 0x09,
100  REG_INT_STATUS_1 = 0x0a,
101  REG_INT_STATUS_2 = 0x0b,
102  REG_INT_STATUS_3 = 0x0c,
103 
104  // 0x0d reserved
105 
106  REG_FIFO_STATUS = 0x0e,
107 
108  REG_PMU_RANGE = 0x0f,
109  REG_PMU_BW = 0x10,
110  REG_PMU_LPW = 0x11,
111  REG_PMU_LOW_POWER = 0x12,
112 
113  REG_ACC_HBW = 0x13,
114 
115  REG_SOFTRESET = 0x14,
116 
117  // 0x15 reserved
118 
119  REG_INT_EN_0 = 0x16,
120  REG_INT_EN_1 = 0x17,
121  REG_INT_EN_2 = 0x18,
122 
123  REG_INT_MAP_0 = 0x19,
124  REG_INT_MAP_1 = 0x1a,
125  REG_INT_MAP_2 = 0x1b,
126 
127  // 0x1c-0x1d reserved
128 
129  REG_INT_SRC = 0x1e,
130 
131  // 0x1f reserved
132 
133  REG_INT_OUT_CTRL = 0x20,
134  REG_INT_RST_LATCH = 0x21,
135 
136  REG_INT_0 = 0x22,
137  REG_INT_1 = 0x23,
138  REG_INT_2 = 0x24,
139  REG_INT_3 = 0x25,
140  REG_INT_4 = 0x26,
141  REG_INT_5 = 0x27,
142  REG_INT_6 = 0x28,
143  REG_INT_7 = 0x29,
144  REG_INT_8 = 0x2a,
145  REG_INT_9 = 0x2b,
146  REG_INT_A = 0x2c,
147  REG_INT_B = 0x2d,
148  REG_INT_C = 0x2e,
149  REG_INT_D = 0x2f,
150 
151  REG_FIFO_CONFIG_0 = 0x30,
152 
153  // 0x31 reserved
154 
155  REG_PMU_SELFTEST = 0x32,
156 
157  REG_TRIM_NVM_CTRL = 0x33,
158 
159  REG_SPI3_WDT = 0x34,
160 
161  // 0x35 reserved
162 
163  REG_OFC_CTRL = 0x36,
164  REG_OFC_SETTING = 0x37,
165 
166  REG_OFC_OFFSET_X = 0x38,
167  REG_OFC_OFFSET_Y = 0x39,
168  REG_OFC_OFFSET_Z = 0x3a,
169 
170  REG_TRIM_GP0 = 0x3b,
171  REG_TRIM_GP1 = 0x3c,
172 
173  // 0x3d reserved
174 
175  REG_FIFO_CONFIG_1 = 0x3e,
176  REG_FIFO_DATA = 0x3f
177 
178  } BMA250E_REGS_T;
179 
184  typedef enum {
185  ACCD10_LSB_NEW_DATA = 0x01, // data updated since last read
186 
187  // 0x02-0x20 reserved
188 
189  ACCD10_LSB0 = 0x40, // lower 2 bits of LSB data
190  ACCD10_LSB1 = 0x80,
191  _ACCD10_LSB_MASK = 3,
192  _ACCD10_LSB_SHIFT = 6
194 
199  typedef enum {
200  ACCD12_LSB_NEW_DATA = 0x01, // data updated since last read
201 
202  // 0x02-0x08 reserved
203 
204  ACCD12_LSB0 = 0x10, // lower 4 bits of LSB data
205  ACCD12_LSB1 = 0x20,
206  ACCD12_LSB2 = 0x40,
207  ACCD12_LSB3 = 0x80,
208  _ACCD12_LSB_MASK = 15,
209  _ACCD12_LSB_SHIFT = 4
211 
215  typedef enum {
216  INT_STATUS_0_LOW = 0x01,
217  INT_STATUS_0_HIGH = 0x02,
218  INT_STATUS_0_SLOPE = 0x04,
219  INT_STATUS_0_SLO_NOT_MOT = 0x08,
220  INT_STATUS_0_D_TAP = 0x10,
221  INT_STATUS_0_S_TAP = 0x20,
222  INT_STATUS_0_ORIENT = 0x40,
223  INT_STATUS_0_FLAT = 0x80
225 
229  typedef enum {
230  _INT_STATUS_1_RESERVED_BITS = 0x0f | 0x10,
231  // 0x01-0x10 reserved
232  INT_STATUS_1_FIFO_FULL = 0x20,
233  INT_STATUS_1_FIFO_WM = 0x40,
234  INT_STATUS_1_DATA = 0x80 // data ready int
236 
240  typedef enum {
241  INT_STATUS_2_SLOPE_FIRST_X = 0x01,
242  INT_STATUS_2_SLOPE_FIRST_Y = 0x02,
243  INT_STATUS_2_SLOPE_FIRST_Z = 0x04,
244  INT_STATUS_2_SLOPE_SIGN = 0x08,
245  INT_STATUS_2_TAP_FIRST_X = 0x10,
246  INT_STATUS_2_TAP_FIRST_Y = 0x20,
247  INT_STATUS_2_TAP_FIRST_Z = 0x40,
248  INT_STATUS_2_TAP_SIGN = 0x80
250 
254  typedef enum {
255  INT_STATUS_3_HIGH_FIRST_X = 0x01,
256  INT_STATUS_3_HIGH_FIRST_Y = 0x02,
257  INT_STATUS_3_HIGH_FIRST_Z = 0x04,
258  INT_STATUS_3_HIGH_SIGN = 0x08,
259 
260  INT_STATUS_3_ORIENT0 = 0x10,
261  INT_STATUS_3_ORIENT1 = 0x20,
262  INT_STATUS_3_ORIENT2 = 0x40,
263  _INT_STATUS_3_ORIENT_MASK = 7,
264  _INT_STATUS_3_ORIENT_SHIFT = 4,
265 
266  INT_STATUS_3_FLAT = 0x80
268 
272  typedef enum {
273  ORIENT_POTRAIT_UPRIGHT = 0,
274  ORIENT_POTRAIT_UPSIDE_DOWN = 1,
275  ORIENT_LANDSCAPE_LEFT = 2,
276  ORIENT_LANDSCAPE_RIGHT = 3,
277  } ORIENT_T;
278 
282  typedef enum {
283  FIFO_STATUS_FRAME_COUNTER0 = 0x01,
284  FIFO_STATUS_FRAME_COUNTER1 = 0x02,
285  FIFO_STATUS_FRAME_COUNTER2 = 0x04,
286  FIFO_STATUS_FRAME_COUNTER3 = 0x08,
287  FIFO_STATUS_FRAME_COUNTER4 = 0x10,
288  FIFO_STATUS_FRAME_COUNTER5 = 0x20,
289  FIFO_STATUS_FRAME_COUNTER6 = 0x40,
290  _FIFO_STATUS_FRAME_COUNTER_MASK = 127,
291  _FIFO_STATUS_FRAME_COUNTER_SHIFT = 0,
292 
293  FIFO_STATUS_FIFO_OVERRUN = 0x80
295 
299  typedef enum {
300  PMU_RANGE0 = 0x01,
301  PMU_RANGE1 = 0x02,
302  PMU_RANGE2 = 0x04,
303  PMU_RANGE3 = 0x08,
304  _PMU_RANGE_MASK = 15,
305  _PMU_RANGE_SHIFT = 0
306 
307  // 0x10-0x80 reserved
309 
313  typedef enum {
314  RANGE_2G = 3,
315  RANGE_4G = 5,
316  RANGE_8G = 8,
317  RANGE_16G = 12
318  } RANGE_T;
319 
323  typedef enum {
324  PMU_BW0 = 0x01,
325  PMU_BW1 = 0x02,
326  PMU_BW2 = 0x04,
327  PMU_BW3 = 0x08,
328  PMU_BW4 = 0x10,
329  _PMU_BW_MASK = 31,
330  _PMU_BW_SHIFT = 0
331 
332  // 0x20-0x80 reserved
333  } PMU_BW_BITS_T;
334 
338  typedef enum {
339  BW_7_81 = 8, // 7.81 Hz
340  BW_15_63 = 9,
341  BW_31_25 = 10,
342  BW_62_5 = 11,
343  BW_125 = 12,
344  BW_250 = 13,
345  BW_500 = 14,
346  BW_1000 = 15
347  } BW_T;
348 
352  typedef enum {
353  // 0x01 reserved
354  _PMU_LPW_RESERVED_MASK = 0x01,
355 
356  PMU_LPW_SLEEP_DUR0 = 0x02, // sleep dur in low power mode
357  PMU_LPW_SLEEP_DUR1 = 0x04,
358  PMU_LPW_SLEEP_DUR2 = 0x08,
359  PMU_LPW_SLEEP_DUR3 = 0x10,
360  _PMU_LPW_SLEEP_MASK = 15,
361  _PMU_LPW_SLEEP_SHIFT = 1,
362 
363  // These are separate bits, deep_suspend, lowpower_en and
364  // suspend (and if all 0, normal). Since only specific
365  // combinations are allowed, we will treat this as a 3 bit
366  // bitfield called POWER_MODE.
367  PMU_LPW_POWER_MODE0 = 0x20, // deep_suspend
368  PMU_LPW_POWER_MODE1 = 0x40, // lowpower_en
369  PMU_LPW_POWER_MODE2 = 0x80, // suspend
370  _PMU_LPW_POWER_MODE_MASK = 7,
371  _PMU_LPW_POWER_MODE_SHIFT = 5
372  } PMU_LPW_BITS_T;
373 
377  typedef enum {
378  SLEEP_DUR_0_5 = 0, // 0.5ms
379  SLEEP_DUR_1 = 6,
380  SLEEP_DUR_2 = 7,
381  SLEEP_DUR_4 = 8,
382  SLEEP_DUR_6 = 9,
383  SLEEP_DUR_10 = 10,
384  SLEEP_DUR_25 = 11,
385  SLEEP_DUR_50 = 12,
386  SLEEP_DUR_100 = 13,
387  SLEEP_DUR_500 = 14,
388  SLEEP_DUR_1000 = 15
389  } SLEEP_DUR_T;
390 
394  typedef enum {
395  POWER_MODE_NORMAL = 0,
396  POWER_MODE_DEEP_SUSPEND = 1,
397  POWER_MODE_LOW_POWER = 2,
398  POWER_MODE_SUSPEND = 4
399  } POWER_MODE_T;
400 
404  typedef enum {
405  _LOW_POWER_RESERVED_BITS = 0x0f | 0x10 | 0x80,
406 
407  // 0x01-0x10 reserved
408  LOW_POWER_SLEEPTIMER_MODE = 0x20,
409  LOW_POWER_LOWPOWER_MODE = 0x40 // LPM1 or LPM2 mode. see DS.
410  // 0x80 reserved
412 
416  typedef enum {
417  _ACC_HBW_RESERVED_BITS = 0x0f | 0x10 | 0x20,
418 
419  // 0x01-0x20 reserved
420  ACC_HBW_SHADOW_DIS = 0x40,
421  ACC_HBW_DATA_HIGH_BW = 0x80
422  } ACC_HBW_BITS_T;
423 
427  typedef enum {
428  _INT_EN_0_RESERVED_BITS = 0x08,
429 
430  INT_EN_0_SLOPE_EN_X = 0x01,
431  INT_EN_0_SLOPE_EN_Y = 0x02,
432  INT_EN_0_SLOPE_EN_Z = 0x04,
433 
434  // 0x08 reserved
435 
436  INT_EN_0_D_TAP_EN = 0x10,
437  INT_EN_0_S_TAP_EN = 0x20,
438  INT_EN_0_ORIENT_EN = 0x40,
439  INT_EN_0_FLAT_EN = 0x80
440  } INT_EN_0_BITS_T;
441 
445  typedef enum {
446  _INT_EN_1_RESERVED_BITS = 0x80,
447 
448  INT_EN_1_HIGH_EN_X = 0x01,
449  INT_EN_1_HIGH_EN_Y = 0x02,
450  INT_EN_1_HIGH_EN_Z = 0x04,
451  INT_EN_1_LOW_EN = 0x08,
452  INT_EN_1_DATA_EN = 0x10,
453  INT_EN_1_INT_FFULL_EN = 0x20, // fifo full
454  INT_EN_1_INT_FWM_EN = 0x40 // fifo watermark
455 
456  // 0x80 reserved
457  } INT_EN_1_BITS_T;
458 
462  typedef enum {
463  _INT_EN_2_RESERVED_BITS = 0xf0,
464 
465  INT_EN_2_SLO_NO_MOT_EN_X = 0x01,
466  INT_EN_2_SLO_NO_MOT_EN_Y = 0x02,
467  INT_EN_2_SLO_NO_MOT_EN_Z = 0x04,
468  INT_EN_2_SLO_NO_MOT_SEL = 0x08
469 
470  // 0x10-0x80 reserved
471  } INT_EN_2_BITS_T;
472 
476  typedef enum {
477  INT_MAP_0_INT1_LOW = 0x01,
478  INT_MAP_0_INT1_HIGH = 0x02,
479  INT_MAP_0_INT1_SLOPE = 0x04,
480  INT_MAP_0_INT1_SLO_NO_MOT = 0x08,
481  INT_MAP_0_INT1_D_TAP = 0x10,
482  INT_MAP_0_INT1_S_TAP = 0x20,
483  INT_MAP_0_INT1_ORIENT = 0x40,
484  INT_MAP_0_INT1_FLAT = 0x80
486 
490  typedef enum {
491  _INT_MAP_1_INT1_RESERVED_BITS = 0x08 | 0x10,
492 
493  INT_MAP_1_INT1_DATA = 0x01,
494  INT_MAP_1_INT1_FWM = 0x02,
495  INT_MAP_1_INT1_FFULL = 0x04,
496 
497  // 0x08-0x10 reserved
498 
499  INT_MAP_1_INT2_FFULL = 0x20,
500  INT_MAP_1_INT2_FWM = 0x40,
501  INT_MAP_1_INT2_DATA = 0x80
503 
507  typedef enum {
508  INT_MAP_2_INT2_LOW = 0x01,
509  INT_MAP_2_INT2_HIGH = 0x02,
510  INT_MAP_2_INT2_SLOPE = 0x04,
511  INT_MAP_2_INT2_SLO_NO_MOT = 0x08,
512  INT_MAP_2_INT2_D_TAP = 0x10,
513  INT_MAP_2_INT2_S_TAP = 0x20,
514  INT_MAP_2_INT2_ORIENT = 0x40,
515  INT_MAP_2_INT2_FLAT = 0x80
517 
521  typedef enum {
522  _INT_SRC_RESERVED_BITS = 0x40 | 0x80,
523 
524  INT_SRC_LOW = 0x01,
525  INT_SRC_HIGH = 0x02,
526  INT_SRC_SLO_NO_MOT = 0x04,
527  INT_SRC_SLOPE = 0x08,
528  INT_SRC_TAP = 0x10,
529  INT_SRC_DATA = 0x20
530 
531  // 0x40-0x80 reserved
532  } INT_SRC_BITS_T;
533 
537  typedef enum {
538  _INT_OUT_CTRL_INT1_RESERVED_BITS = 0xf0,
539 
540  INT_OUT_CTRL_INT1_LVL = 0x01, // level or edge
541  INT_OUT_CTRL_INT1_OD = 0x02, // push-pull or open drain
542  INT_OUT_CTRL_INT2_LVL = 0x04,
543  INT_OUT_CTRL_INT2_OD = 0x08
544 
545  // 0x10-0x80 reserved
547 
551  typedef enum {
552  _INT_RST_LATCH_RESERVED_BITS = 0x10 | 0x20 | 0x40,
553 
554  INT_RST_LATCH0 = 0x01,
555  INT_RST_LATCH1 = 0x02,
556  INT_RST_LATCH2 = 0x04,
557  INT_RST_LATCH3 = 0x08,
558  _INT_RST_LATCH_MASK = 15,
559  _INT_RST_LATCH_SHIFT = 0,
560 
561  // 0x10-0x40 reserved
562 
563  INT_RST_LATCH_RESET_INT = 0x80
565 
569  typedef enum {
570  RST_LATCH_NON_LATCHED = 0,
571  RST_LATCH_TEMPORARY_250MS = 1,
572  RST_LATCH_TEMPORARY_500MS = 2,
573  RST_LATCH_TEMPORARY_1S = 3,
574  RST_LATCH_TEMPORARY_2S = 4,
575  RST_LATCH_TEMPORARY_4S = 5,
576  RST_LATCH_TEMPORARY_8S = 6,
577  RST_LATCH_LATCHED = 7,
578 
579  // 8 == non latched
580 
581  RST_LATCH_TEMPORARY_250US = 9,
582  RST_LATCH_TEMPORARY_500US = 10,
583  RST_LATCH_TEMPORARY_1MS = 11,
584  RST_LATCH_TEMPORARY_12_5MS = 12,
585  RST_LATCH_TEMPORARY_25MS = 13,
586  RST_LATCH_TEMPORARY_50MS = 14
587 
588  // 15 == latched
589  } RST_LATCH_T;
590 
594  typedef enum {
595  INT_2_LOW_HY0 = 0x01,
596  INT_2_LOW_HY1 = 0x02,
597  _INT_2_LOW_HY_MASK = 3,
598  _INT_2_LOW_HY_SHIFT = 0,
599 
600  INT_2_LOW_MODE = 0x04,
601 
602  // 0x08-0x20 reserved
603 
604  INT_2_HIGH_HY0 = 0x40,
605  INT_2_HIGH_HY1 = 0x80,
606  _INT_2_HIGH_HY_MASK = 3,
607  _INT_2_HIGH_HY_SHIFT = 6
608  } INT_2_BITS_T;
609 
613  typedef enum {
614  INT_5_SLOPE_DUR0 = 0x01,
615  INT_5_SLOPE_DUR1 = 0x02,
616  _INT_5_SLOPE_DUR_MASK = 3,
617  _INT_5_SLOPE_DUR_SHIFT = 0,
618 
619  INT_5_SLO_NO_MOT_DUR0 = 0x04,
620  INT_5_SLO_NO_MOT_DUR1 = 0x08,
621  INT_5_SLO_NO_MOT_DUR2 = 0x10,
622  INT_5_SLO_NO_MOT_DUR3 = 0x20,
623  INT_5_SLO_NO_MOT_DUR4 = 0x40,
624  INT_5_SLO_NO_MOT_DUR5 = 0x80,
625  _INT_5_SLO_NO_MOT_DUR_MASK = 63,
626  _INT_5_SLO_NO_MOT_DUR_SHIFT = 2
627  } INT_5_BITS_T;
628 
632  typedef enum {
633  INT_8_TAP_DUR0 = 0x01,
634  INT_8_TAP_DUR1 = 0x02,
635  INT_8_TAP_DUR2 = 0x04,
636  _INT_8_TAP_DUR_MASK = 7,
637  _INT_8_TAP_DUR_SHIFT = 0,
638 
639  // 0x08-0x20 reserved
640 
641  INT_8_TAP_SHOCK = 0x40,
642  INT_8_TAP_QUIET = 0x80
643  } INT_8_BITS_T;
644 
648  typedef enum {
649  INT_9_TAP_TH0 = 0x01,
650  INT_9_TAP_TH1 = 0x02,
651  INT_9_TAP_TH2 = 0x04,
652  INT_9_TAP_TH3 = 0x08,
653  INT_9_TAP_TH4 = 0x10,
654  _INT_5_TAP_TH_MASK = 31,
655  _INT_5_TAP_TH_SHIFT = 0,
656 
657  // 0x20 reserved
658 
659  INT_9_TAP_SAMP0 = 0x40,
660  INT_9_TAP_SAMP1 = 0x80,
661  INT_9_TAP_SAMP1_MASK = 3,
662  INT_9_TAP_SAMP1_SHIFT = 6
663  } INT_9_BITS_T;
664 
668  typedef enum {
669  INT_A_ORIENT_MODE0 = 0x01,
670  INT_A_ORIENT_MODE1 = 0x02,
671  _INT_A_ORIENT_MODE_MASK = 3,
672  _INT_A_ORIENT_MODE_SHIFT = 0,
673 
674  INT_A_ORIENT_BLOCKING0 = 0x04,
675  INT_A_ORIENT_BLOCKING1 = 0x08,
676  _INT_A_ORIENT_BLOCKING_MASK = 3,
677  _INT_A_ORIENT_BLOCKING_SHIFT = 2,
678 
679  INT_A_ORIENT_HYST0 = 0x10,
680  INT_A_ORIENT_HYST1 = 0x20,
681  INT_A_ORIENT_HYST2 = 0x40,
682  _INT_A_ORIENT_HYST_MASK = 7,
683  _INT_A_ORIENT_HYST_SHIFT = 4
684 
685  // 0x80 reserved
686  } INT_A_BITS_T;
687 
691  typedef enum {
692  ORIENT_MODE_SYMETRICAL = 0,
693  ORIENT_MODE_HIGH_ASYMETRICAL = 1,
694  ORIENT_MODE_LOW_ASYMETRICAL = 2
695  } ORIENT_MODE_T;
696 
700  typedef enum {
701  ORIENT_BLOCKING_NONE = 0,
702  ORIENT_BLOCKING_THETA_ACC_1_5G = 1,
703  ORIENT_BLOCKING_THETA_ACC_0_2G_1_5G = 2,
704  ORIENT_BLOCKING_THETA_ACC_0_4G_1_5G = 3
706 
710  typedef enum {
711  INT_B_ORIENT_THETA0 = 0x01,
712  INT_B_ORIENT_THETA1 = 0x02,
713  INT_B_ORIENT_THETA2 = 0x04,
714  INT_B_ORIENT_THETA3 = 0x08,
715  INT_B_ORIENT_THETA4 = 0x10,
716  INT_B_ORIENT_THETA5 = 0x20,
717  _INT_B_ORIENT_THETA_MASK = 63,
718  _INT_B_ORIENT_THETA_SHIFT = 0,
719 
720  INT_B_ORIENT_UD_EN = 0x40
721  // 0x80 reserved
722  } INT_B_BITS_T;
723 
727  typedef enum {
728  INT_B_FLAT_THETA0 = 0x01,
729  INT_B_FLAT_THETA1 = 0x02,
730  INT_B_FLAT_THETA2 = 0x04,
731  INT_B_FLAT_THETA3 = 0x08,
732  INT_B_FLAT_THETA4 = 0x10,
733  INT_B_FLAT_THETA5 = 0x20,
734  _INT_B_FLAT_THETA_MASK = 63,
735  _INT_B_FLAT_THETA_SHIFT = 0,
736 
737  // 0x40-0x80 reserved
738  } INT_C_BITS_T;
739 
743  typedef enum {
744  INT_D_FLAT_HY0 = 0x01,
745  INT_D_FLAT_HY1 = 0x02,
746  INT_D_FLAT_HY2 = 0x04,
747  _INT_B_FLAT_HY_MASK = 7,
748  _INT_B_FLAT_HY_SHIFT = 0,
749 
750  // 0x08 reserved
751 
752  INT_D_FLAT_HOLD_TIME0 = 0x10,
753  INT_D_FLAT_HOLD_TIME1 = 0x20,
754  _INT_B_FLAT_HOLD_TIME_MASK = 3,
755  _INT_B_FLAT_HOLD_TIME_SHIFT = 4
756 
757  // 0x40-0x80 reserved
758  } INT_D_BITS_T;
759 
763  typedef enum {
764  _FIFO_CONFIG_0_RESERVED_BITS = 0x80 | 0x40,
765 
766  FIFO_CONFIG_0_WATER_MARK0 = 0x01,
767  FIFO_CONFIG_0_WATER_MARK1 = 0x02,
768  FIFO_CONFIG_0_WATER_MARK2 = 0x04,
769  FIFO_CONFIG_0_WATER_MARK3 = 0x08,
770  FIFO_CONFIG_0_WATER_MARK4 = 0x10,
771  FIFO_CONFIG_0_WATER_MARK5 = 0x20,
772  _FIFO_CONFIG_0_WATER_MARK_MASK = 63,
773  _FIFO_CONFIG_0_WATER_MARK_SHIFT = 0
775 
779  typedef enum {
780  PMU_SELFTTEST_AXIS0 = 0x01,
781  PMU_SELFTTEST_AXIS1 = 0x02,
782  _PMU_SELFTTEST_AXIS_MASK = 3,
783  _PMU_SELFTTEST_AXIS_SHIFT = 0,
784 
785  PMU_SELFTTEST_SIGN = 0x04,
786 
787  // 0x08 reserved
788 
789  PMU_SELFTTEST_AMP = 0x10,
790 
791  // 0x20-0x80 reserved
793 
797  typedef enum {
798  SELFTTEST_AXIS_NONE = 0,
799  SELFTTEST_AXIS_X = 1,
800  SELFTTEST_AXIS_Y = 2,
801  SELFTTEST_AXIS_Z = 3,
803 
807  typedef enum {
808  TRIM_NVM_CTRL_NVM_PROG_MODE = 0x01,
809  TRIM_NVM_CTRL_NVM_PROG_TRIG = 0x02,
810  TRIM_NVM_CTRL_NVM_PROG_RDY = 0x04,
811  TRIM_NVM_CTRL_NVM_PROG_LOAD = 0x08,
812 
813  TRIM_NVM_CTRL_NVM_REMAIN0 = 0x10,
814  TRIM_NVM_CTRL_NVM_REMAIN1 = 0x20,
815  TRIM_NVM_CTRL_NVM_REMAIN2 = 0x40,
816  TRIM_NVM_CTRL_NVM_REMAIN3 = 0x80,
817  _TRIM_NVM_CTRL_NVM_REMAIN_MASK = 15,
818  _TRIM_NVM_CTRL_NVM_REMAIN_SHIFT = 4
820 
824  typedef enum {
825  _SPI3_WDT_RESERVED_BITS = 0xf0 | 0x08,
826 
827  SPI3_WDT_SPI3 = 0x01, // 3-wire SPI - NOT SUPPORTED
828 
829  SPI3_WDT_I2C_WDT_SEL = 0x02,
830  SPI3_WDT_I2C_WDT_EN = 0x04
831 
832  // 0x08-0x80 reserved
833  } SPI3_WDT_BITS_T;
834 
838  typedef enum {
839  OFC_CTRL_HP_X_EN = 0x01,
840  OFC_CTRL_HP_Y_EN = 0x02,
841  OFC_CTRL_HP_Z_EN = 0x04,
842 
843  // 0x08 reserved
844 
845  OFC_CTRL_CAL_RDY = 0x10,
846 
847  OFC_CTRL_CAL_TRIGGER0 = 0x20,
848  OFC_CTRL_CAL_TRIGGER1 = 0x40,
849  _OFC_CTRL_CAL_TRIGGER_MASK = 3,
850  _OFC_CTRL_CAL_TRIGGER_SHIFT = 5,
851 
852  OFC_CTRL_OFFSET_RESET = 0x80
853 
854  } OFC_CTRL_BITS_T;
855 
859  typedef enum {
860  CAL_TRIGGER_NONE = 0,
861  CAL_TRIGGER_X = 1,
862  CAL_TRIGGER_Y = 2,
863  CAL_TRIGGER_Z = 3
864  } CAL_TRIGGER_T;
865 
869  typedef enum {
870  OFC_SETTING_CUT_OFF = 0x01,
871 
872  OFC_SETTING_OFFSET_TARGET_X0 = 0x02,
873  OFC_SETTING_OFFSET_TARGET_X1 = 0x04,
874  _OFC_SETTING_OFFSET_TARGET_X_MASK = 3,
875  _OFC_SETTING_OFFSET_TARGET_X_SHIFT = 1,
876 
877  OFC_SETTING_OFFSET_TARGET_Y0 = 0x08,
878  OFC_SETTING_OFFSET_TARGET_Y1 = 0x10,
879  _OFC_SETTING_OFFSET_TARGET_Y_MASK = 3,
880  _OFC_SETTING_OFFSET_TARGET_Y_SHIFT = 3,
881 
882  OFC_SETTING_OFFSET_TARGET_Z0 = 0x20,
883  OFC_SETTING_OFFSET_TARGET_Z1 = 0x40,
884  _OFC_SETTING_OFFSET_TARGET_Z_MASK = 3,
885  _OFC_SETTING_OFFSET_TARGET_Z_SHIFT = 5
886 
887  // 0x80 reserved
889 
893  typedef enum {
894  OFFSET_TARGET_0G = 0,
895  OFFSET_TARGET_PLUS_1G = 1,
896  OFFSET_TARGET_MINUS_1G = 2,
897  // 3 == 0G
898  } OFFSET_TARGET_T;
899 
903  typedef enum {
904  FIFO_CONFIG_1_FIFO_DATA_SEL0 = 0x01,
905  FIFO_CONFIG_1_FIFO_DATA_SEL1 = 0x02,
906  _FIFO_CONFIG_1_FIFO_DATA_SEL = 3,
907  _FIFO_CONFIG_1_FIFO_DATA_SHIFT = 0,
908 
909  // 0x04-0x20 reserved
910 
911  FIFO_CONFIG_1_FIFO_MODE0 = 0x40,
912  FIFO_CONFIG_1_FIFO_MODE1 = 0x80,
913  _FIFO_CONFIG_1_FIFO_MODE_MASK = 3,
914  _FIFO_CONFIG_1_FIFO_MODE_SHIFT = 5
916 
920  typedef enum {
921  FIFO_DATA_SEL_XYZ = 0,
922  FIFO_DATA_SEL_X = 1,
923  FIFO_DATA_SEL_Y = 2,
924  FIFO_DATA_SEL_Z = 3
925  } FIFO_DATA_SEL_T;
926 
930  typedef enum {
931  FIFO_MODE_BYPASS = 0,
932  FIFO_MODE_FIFO = 1,
933  FIFO_MODE_STREAM = 2
934 
935  // 3 == reserved (execute self-destruct :)
936  } FIFO_MODE_T;
937 
938  // interrupt selection for installISR() and uninstallISR()
939  typedef enum {
940  INTERRUPT_INT1,
941  INTERRUPT_INT2
942  } INTERRUPT_PINS_T;
943 
944  // Different variants of this chip support different resolutions.
945  // The 0xf9 variant supports 10b, while the 0xfa variant (bmx050)
946  // supports 12 bits.
947  typedef enum {
948  RESOLUTION_10BITS,
949  RESOLUTION_12BITS
950  } RESOLUTION_T;
951 
952 
968  BMA250E(int bus=BMA250E_I2C_BUS, int addr=BMA250E_DEFAULT_ADDR,
969  int cs=-1);
970 
974  ~BMA250E();
975 
979  void update();
980 
986  uint8_t getChipID();
987 
999  void getAccelerometer(float *x, float *y, float *z);
1000 
1010  float *getAccelerometer();
1011 
1021  float getTemperature(bool fahrenheit=false);
1022 
1035  void init(POWER_MODE_T pwr=POWER_MODE_NORMAL,
1036  RANGE_T range=RANGE_2G, BW_T bw=BW_250);
1037 
1044  void reset();
1045 
1052  void setRange(RANGE_T range);
1053 
1059  void setBandwidth(BW_T bw);
1060 
1078  void setPowerMode(POWER_MODE_T power);
1079 
1097  void enableFIFO(bool useFIFO);
1098 
1106  void fifoSetWatermark(int wm);
1107 
1116  void fifoConfig(FIFO_MODE_T mode, FIFO_DATA_SEL_T axes);
1117 
1128  void setSelfTest(bool sign, bool amp, SELFTTEST_AXIS_T axis);
1129 
1137  uint8_t getInterruptEnable0();
1138 
1145  void setInterruptEnable0(uint8_t bits);
1146 
1153  uint8_t getInterruptEnable1();
1154 
1161  void setInterruptEnable1(uint8_t bits);
1162 
1169  uint8_t getInterruptEnable2();
1170 
1177  void setInterruptEnable2(uint8_t bits);
1178 
1186  uint8_t getInterruptMap0();
1187 
1195  void setInterruptMap0(uint8_t bits);
1196 
1203  uint8_t getInterruptMap1();
1204 
1211  void setInterruptMap1(uint8_t bits);
1212 
1219  uint8_t getInterruptMap2();
1220 
1227  void setInterruptMap2(uint8_t bits);
1228 
1237  uint8_t getInterruptSrc();
1238 
1247  void setInterruptSrc(uint8_t bits);
1248 
1257  uint8_t getInterruptOutputControl();
1258 
1267  void setInterruptOutputControl(uint8_t bits);
1268 
1272  void clearInterruptLatches();
1273 
1281 
1289 
1297  uint8_t getInterruptStatus0();
1298 
1305  uint8_t getInterruptStatus1();
1306 
1313  uint8_t getInterruptStatus2();
1314 
1323  uint8_t getInterruptStatus3Bits();
1324 
1332 
1344  void enableRegisterShadowing(bool shadow);
1345 
1354  void enableOutputFiltering(bool filter);
1355 
1362  void setLowPowerMode2();
1363 
1364 
1365 #if defined(SWIGJAVA) || defined(JAVACALLBACK)
1366  void installISR(INTERRUPT_PINS_T intr, int gpio, mraa::Edge level,
1367  jobject runnable);
1368 #else
1369 
1381  void installISR(INTERRUPT_PINS_T intr, int gpio, mraa::Edge level,
1382  void (*isr)(void *), void *arg);
1383 #endif
1384 
1391  void uninstallISR(INTERRUPT_PINS_T intr);
1392 
1399  uint8_t readReg(uint8_t reg);
1400 
1408  int readRegs(uint8_t reg, uint8_t *buffer, int len);
1409 
1416  void writeReg(uint8_t reg, uint8_t val);
1417 
1418  protected:
1419  mraa::I2c *m_i2c;
1420  mraa::Spi *m_spi;
1421 
1422  mraa::Gpio *m_gpioIntr1;
1423  mraa::Gpio *m_gpioIntr2;
1424 
1425  // spi chip select
1426  mraa::Gpio *m_gpioCS;
1427 
1428  uint8_t m_addr;
1429  RESOLUTION_T m_resolution;
1430 
1431  // does this chip support the fifo?
1432  bool m_fifoAvailable;
1433 
1434  // SPI chip select
1435  void csOn();
1436  void csOff();
1437 
1438  // acc data
1439  float m_accX;
1440  float m_accY;
1441  float m_accZ;
1442 
1443  float m_accScale;
1444 
1445  float m_temperature;
1446 
1447  private:
1448  bool m_isSPI;
1449 
1450  // use the FIFO by default?
1451  bool m_useFIFO;
1452 
1453  // return a reference to a gpio pin pointer depending on intr
1454  mraa::Gpio*& getPin(INTERRUPT_PINS_T intr);
1455 
1456  // Adding a private function definition for java bindings
1457 #if defined(SWIGJAVA) || defined(JAVACALLBACK)
1458  void installISR(INTERRUPT_PINS_T intr, int gpio, mraa::Edge level,
1459  void (*isr)(void *), void *arg);
1460 #endif
1461  };
1462 }
INT_STATUS_2_BITS_T
Definition: bma250e.hpp:240
ORIENT_MODE_T
Definition: bma250e.hpp:691
INT_MAP_0_BITS_T
Definition: bma250e.hpp:476
void fifoSetWatermark(int wm)
Definition: bma250e.cxx:458
int readRegs(uint8_t reg, uint8_t *buffer, int len)
Definition: bma250e.cxx:279
uint8_t getInterruptEnable0()
Definition: bma250e.cxx:495
INT_5_BITS_T
Definition: bma250e.hpp:613
RST_LATCH_T
Definition: bma250e.hpp:569
void setInterruptSrc(uint8_t bits)
Definition: bma250e.cxx:568
INT_9_BITS_T
Definition: bma250e.hpp:648
INT_EN_1_BITS_T
Definition: bma250e.hpp:445
CAL_TRIGGER_T
Definition: bma250e.hpp:859
void init(POWER_MODE_T pwr=POWER_MODE_NORMAL, RANGE_T range=RANGE_2G, BW_T bw=BW_250)
Definition: bma250e.cxx:144
void setInterruptMap1(uint8_t bits)
Definition: bma250e.cxx:546
ORIENT_T
Definition: bma250e.hpp:272
INT_STATUS_0_BITS_T
Definition: bma250e.hpp:215
uint8_t getInterruptEnable2()
Definition: bma250e.cxx:519
void setBandwidth(BW_T bw)
Definition: bma250e.cxx:442
void enableRegisterShadowing(bool shadow)
Definition: bma250e.cxx:615
void writeReg(uint8_t reg, uint8_t val)
Definition: bma250e.cxx:313
uint8_t readReg(uint8_t reg)
Definition: bma250e.cxx:257
void setInterruptEnable0(uint8_t bits)
Definition: bma250e.cxx:500
uint8_t getInterruptSrc()
Definition: bma250e.cxx:563
BW_T
Definition: bma250e.hpp:338
void setRange(RANGE_T range)
Definition: bma250e.cxx:390
PMU_BW_BITS_T
Definition: bma250e.hpp:323
INT_D_BITS_T
Definition: bma250e.hpp:743
void setInterruptOutputControl(uint8_t bits)
Definition: bma250e.cxx:580
float getTemperature(bool fahrenheit=false)
Definition: bma250e.cxx:376
void setLowPowerMode2()
Definition: bma250e.cxx:672
uint8_t getInterruptMap2()
Definition: bma250e.cxx:553
void setInterruptMap0(uint8_t bits)
Definition: bma250e.cxx:536
ACCD12_LSB_BITS_T
Definition: bma250e.hpp:199
uint8_t getInterruptStatus0()
Definition: bma250e.cxx:639
void reset()
Definition: bma250e.cxx:384
INT_OUT_CTRL_BITS_T
Definition: bma250e.hpp:537
SELFTTEST_AXIS_T
Definition: bma250e.hpp:797
RST_LATCH_T getInterruptLatchBehavior()
Definition: bma250e.cxx:596
POWER_MODE_T
Definition: bma250e.hpp:394
INT_2_BITS_T
Definition: bma250e.hpp:594
INT_C_BITS_T
Definition: bma250e.hpp:727
INT_8_BITS_T
Definition: bma250e.hpp:632
SLEEP_DUR_T
Definition: bma250e.hpp:377
INT_STATUS_1_BITS_T
Definition: bma250e.hpp:229
float * getAccelerometer()
Definition: bma250e.cxx:368
ACCD10_LSB_BITS_T
Definition: bma250e.hpp:184
PMU_RANGE_BITS_T
Definition: bma250e.hpp:299
void setInterruptEnable1(uint8_t bits)
Definition: bma250e.cxx:512
ACC_HBW_BITS_T
Definition: bma250e.hpp:416
uint8_t getInterruptStatus2()
Definition: bma250e.cxx:649
INT_STATUS_3_BITS_T
Definition: bma250e.hpp:254
INT_RST_LATCH_BITS_T
Definition: bma250e.hpp:551
~BMA250E()
Definition: bma250e.cxx:131
OFFSET_TARGET_T
Definition: bma250e.hpp:893
INT_MAP_1_BITS_T
Definition: bma250e.hpp:490
BMA250E_REGS_T
Definition: bma250e.hpp:85
FIFO_STATUS_BITS_T
Definition: bma250e.hpp:282
OFC_CTRL_BITS_T
Definition: bma250e.hpp:838
void clearInterruptLatches()
Definition: bma250e.cxx:587
void setInterruptEnable2(uint8_t bits)
Definition: bma250e.cxx:524
RANGE_T
Definition: bma250e.hpp:313
OFC_SETTING_BITS_T
Definition: bma250e.hpp:869
void setSelfTest(bool sign, bool amp, SELFTTEST_AXIS_T axis)
Definition: bma250e.cxx:482
uint8_t getInterruptStatus1()
Definition: bma250e.cxx:644
void fifoConfig(FIFO_MODE_T mode, FIFO_DATA_SEL_T axes)
Definition: bma250e.cxx:470
void update()
Definition: bma250e.cxx:173
void enableFIFO(bool useFIFO)
Definition: bma250e.cxx:251
PMU_SELFTTEST_BITS_T
Definition: bma250e.hpp:779
FIFO_MODE_T
Definition: bma250e.hpp:930
API for the BMA250E 10 bit Triaxial Accelerometer.
Definition: bma250e.hpp:72
void setInterruptLatchBehavior(RST_LATCH_T latch)
Definition: bma250e.cxx:605
ORIENT_T getInterruptStatus3Orientation()
Definition: bma250e.cxx:661
LOW_POWER_BITS_T
Definition: bma250e.hpp:404
PMU_LPW_BITS_T
Definition: bma250e.hpp:352
void setInterruptMap2(uint8_t bits)
Definition: bma250e.cxx:558
void setPowerMode(POWER_MODE_T power)
Definition: bma250e.cxx:447
TRIM_NVM_CTRL_BITS_T
Definition: bma250e.hpp:807
ORIENT_BLOCKING_T
Definition: bma250e.hpp:700
INT_MAP_2_BITS_T
Definition: bma250e.hpp:507
SPI3_WDT_BITS_T
Definition: bma250e.hpp:824
uint8_t getInterruptMap0()
Definition: bma250e.cxx:531
INT_B_BITS_T
Definition: bma250e.hpp:710
void installISR(INTERRUPT_PINS_T intr, int gpio, mraa::Edge level, void(*isr)(void *), void *arg)
Definition: bma250e.cxx:700
uint8_t getInterruptStatus3Bits()
Definition: bma250e.cxx:654
uint8_t getChipID()
Definition: bma250e.cxx:351
INT_EN_2_BITS_T
Definition: bma250e.hpp:462
FIFO_DATA_SEL_T
Definition: bma250e.hpp:920
BMA250E(int bus=BMA250E_I2C_BUS, int addr=BMA250E_DEFAULT_ADDR, int cs=-1)
Definition: bma250e.cxx:43
void enableOutputFiltering(bool filter)
Definition: bma250e.cxx:627
INT_SRC_BITS_T
Definition: bma250e.hpp:521
void uninstallISR(INTERRUPT_PINS_T intr)
Definition: bma250e.cxx:714
FIFO_CONFIG_0_BITS_T
Definition: bma250e.hpp:763
uint8_t getInterruptMap1()
Definition: bma250e.cxx:541
FIFO_CONFIG_1_BITS_T
Definition: bma250e.hpp:903
INT_A_BITS_T
Definition: bma250e.hpp:668
uint8_t getInterruptEnable1()
Definition: bma250e.cxx:507
INT_EN_0_BITS_T
Definition: bma250e.hpp:427
uint8_t getInterruptOutputControl()
Definition: bma250e.cxx:575