upm  1.1.0
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bmg160.hpp
1 /*
2  * Author: Jon Trulson <jtrulson@ics.com>
3  * Copyright (c) 2016 Intel Corporation.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be
14  * included in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
17  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
19  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
20  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
21  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
22  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  */
24 #pragma once
25 
26 #include <string>
27 #include <mraa/i2c.hpp>
28 #include <mraa/spi.hpp>
29 #include <mraa/gpio.hpp>
30 
31 #define BMG160_I2C_BUS 0
32 #define BMG160_SPI_BUS 0
33 #define BMG160_DEFAULT_ADDR 0x68
34 
35 
36 namespace upm {
37 
70  class BMG160 {
71  public:
72  // special reset byte
73  static const uint8_t BMG160_RESET_BYTE = 0xb6;
74 
75  // NOTE: Reserved registers must not be written into. Reading
76  // from them may return indeterminate values. Registers
77  // containing reserved bitfields must be written as 0. Reading
78  // reserved bitfields may return indeterminate values.
79 
83  typedef enum : uint8_t {
84  REG_CHIP_ID = 0x00,
85 
86  // 0x01 reserved
87 
88  REG_RATE_X_LSB = 0x02,
89  REG_RATE_X_MSB = 0x03,
90  REG_RATE_Y_LSB = 0x04,
91  REG_RATE_Y_MSB = 0x05,
92  REG_RATE_Z_LSB = 0x06,
93  REG_RATE_Z_MSB = 0x07,
94 
95  REG_TEMP = 0x08,
96 
97  REG_INT_STATUS_0 = 0x09,
98  REG_INT_STATUS_1 = 0x0a,
99  REG_INT_STATUS_2 = 0x0b,
100  REG_INT_STATUS_3 = 0x0c,
101 
102  // 0x0d reserved
103 
104  REG_FIFO_STATUS = 0x0e,
105 
106  REG_GYR_RANGE = 0x0f,
107  REG_GYR_BW = 0x10,
108  REG_LPM1 = 0x11,
109  REG_LPM2 = 0x12,
110 
111  REG_RATE_HBW = 0x13,
112 
113  REG_SOFTRESET = 0x14,
114 
115  REG_INT_EN_0 = 0x15,
116  REG_INT_EN_1 = 0x16,
117 
118  REG_INT_MAP_0 = 0x17,
119  REG_INT_MAP_1 = 0x18,
120  REG_INT_MAP_2 = 0x19,
121 
122  REG_INT_1A = 0x1a,
123  REG_INT_1B = 0x1b,
124  REG_INT_1C = 0x1c,
125 
126  // 0x1d reserved
127 
128  REG_INT_1E = 0x1e,
129 
130  // 0x1f-0x20 reserved
131 
132  REG_INT_RST_LATCH = 0x21,
133 
134  REG_HIGH_TH_X = 0x22,
135  REG_HIGH_DUR_X = 0x23,
136  REG_HIGH_TH_Y = 0x24,
137  REG_HIGH_DUR_Y = 0x25,
138  REG_HIGH_TH_Z = 0x26,
139  REG_HIGH_DUR_Z = 0x27,
140 
141  // 0x28-0x30 reserved
142 
143  REG_SOC = 0x31,
144  REG_A_FOC = 0x32,
145 
146  REG_TRIM_NVM_CTRL = 0x33,
147 
148  REG_SPI3_WDT = 0x34,
149 
150  // 0x35 reserved
151 
152  REG_OFC1 = 0x36,
153  REG_OFC2 = 0x37,
154  REG_OFC3 = 0x38,
155  REG_OFC4 = 0x39,
156 
157  REG_TRIM_GP0 = 0x3a,
158  REG_TRIM_GP1 = 0x3b,
159 
160  REG_BIST = 0x3c,
161 
162  REG_FIFO_CONFIG_0 = 0x3d,
163  REG_FIFO_CONFIG_1 = 0x3e,
164 
165  REG_FIFO_DATA = 0x3f
166 
167  } BMG160_REGS_T;
168 
172  typedef enum {
173  _INT_STATUS_0_RESERVED_BITS = 0xf0 | 0x08 | 0x01,
174 
175  INT_STATUS_0_HIGH_INT = 0x02,
176  INT_STATUS_0_ANY_INT = 0x04
178 
182  typedef enum {
183  _INT_STATUS_1_RESERVED_BITS = 0x0f,
184 
185  INT_STATUS_1_FIFO_INT = 0x10,
186  INT_STATUS_1_FAST_OFFSET_INT = 0x20,
187  INT_STATUS_1_AUTO_OFFSET_INT = 0x40,
188  INT_STATUS_1_DATA_INT = 0x80
190 
194  typedef enum {
195  _INT_STATUS_2_RESERVED_BITS = 0xf0,
196 
197  INT_STATUS_2_ANY_FIRST_X = 0x01,
198  INT_STATUS_2_ANY_FIRST_Y = 0x02,
199  INT_STATUS_2_ANY_FIRST_Z = 0x04,
200  INT_STATUS_2_ANY_SIGN = 0x08
202 
206  typedef enum {
207  _INT_STATUS_3_RESERVED_BITS = 0xf0,
208 
209  INT_STATUS_3_HIGH_FIRST_X = 0x01,
210  INT_STATUS_3_HIGH_FIRST_Y = 0x02,
211  INT_STATUS_3_HIGH_FIRST_Z = 0x04,
212  INT_STATUS_3_HIGH_SIGN = 0x08
214 
218  typedef enum {
219  FIFO_STATUS_FRAME_COUNTER0 = 0x01,
220  FIFO_STATUS_FRAME_COUNTER1 = 0x02,
221  FIFO_STATUS_FRAME_COUNTER2 = 0x04,
222  FIFO_STATUS_FRAME_COUNTER3 = 0x08,
223  FIFO_STATUS_FRAME_COUNTER4 = 0x10,
224  FIFO_STATUS_FRAME_COUNTER5 = 0x20,
225  FIFO_STATUS_FRAME_COUNTER6 = 0x40,
226  _FIFO_STATUS_FRAME_COUNTER_MASK = 127,
227  _FIFO_STATUS_FRAME_COUNTER_SHIFT = 0,
228 
229  FIFO_STATUS_FIFO_OVERRUN = 0x80
231 
235  typedef enum {
236  _GYR_RANGE_RESERVED_BITS = 0x20 | 0x10 | 0x08,
237 
238  GYR_RANGE0 = 0x01,
239  GYR_RANGE1 = 0x02,
240  GYR_RANGE2 = 0x04,
241  _GYR_RANGE_MASK = 7,
242  _GYR_RANGE_SHIFT = 0,
243 
244  GYR_RANGE_FIXED0 = 0x40, // bits need hardcoding to 0b10
245  GYR_RANGE_FIXED1 = 0x80, // for some odd reason...
246  _GYR_RANGE_FIXED_MASK = 3,
247  _GYR_RANGE_FIXED_SHIFT = 6,
248  _GYR_RANGE_FIXED_VALUE = 2 // 0b10
250 
254  typedef enum {
255  RANGE_2000 = 0, // degrees/sec
256  RANGE_1000 = 1,
257  RANGE_500 = 2,
258  RANGE_250 = 3,
259  RANGE_125 = 4
260  } RANGE_T;
261 
265  typedef enum {
266  _GYR_BW_RESERVED_BITS = 0xf0,
267 
268  GYR_BW0 = 0x01,
269  GYR_BW1 = 0x02,
270  GYR_BW2 = 0x04,
271  GYR_BW3 = 0x08,
272  _GYR_BW_MASK = 15,
273  _GYR_BW_SHIFT = 0
274  } GYR_BW_BITS_T;
275 
279  typedef enum {
280  BW_2000_UNFILTERED = 0, // ODR/Filter BW
281  BW_2000_230 = 1, // ODR 2000Hz, Filter BW 230Hz
282  BW_1000_116 = 2,
283  BW_400_47 = 3,
284  BW_200_23 = 4,
285  BW_100_12 = 5,
286  BW_200_64 = 6,
287  BW_100_32 = 7
288  } BW_T;
289 
293  typedef enum {
294  // 0x01 reserved
295  _LPM1_RESERVED_MASK = 0x40 | 0x10 | 0x01,
296 
297  LPM1_SLEEP_DUR0 = 0x02, // sleep dur in low power mode
298  LPM1_SLEEP_DUR1 = 0x04,
299  LPM1_SLEEP_DUR2 = 0x08,
300  _LPM1_SLEEP_MASK = 7,
301  _LPM1_SLEEP_SHIFT = 1,
302 
303  // These are separate bits, deep_suspend and suspend (and if all
304  // 0, normal). Since only specific combinations are allowed, we
305  // will treat this as a 3 bit bitfield called POWER_MODE.
306  LPM1_POWER_MODE0 = 0x20, // deep_suspend
307  LPM1_POWER_MODE1 = 0x40, // must always be 0!
308  LPM1_POWER_MODE2 = 0x80, // suspend
309  _LPM1_POWER_MODE_MASK = 7,
310  _LPM1_POWER_MODE_SHIFT = 5
311  } LPM1_BITS_T;
312 
316  typedef enum {
317  SLEEP_DUR_2 = 0, // 2ms
318  SLEEP_DUR_4 = 1,
319  SLEEP_DUR_5 = 2,
320  SLEEP_DUR_8 = 3,
321  SLEEP_DUR_10 = 4,
322  SLEEP_DUR_15 = 5,
323  SLEEP_DUR_18 = 6,
324  SLEEP_DUR_20 = 7
325  } SLEEP_DUR_T;
326 
330  typedef enum {
331  POWER_MODE_NORMAL = 0,
332  POWER_MODE_DEEP_SUSPEND = 1,
333  POWER_MODE_SUSPEND = 4
334  } POWER_MODE_T;
335 
339  typedef enum {
340  _LPM2_RESERVED_BITS = 0x08,
341 
342  LPM2_AUTOSLEEP_DUR0 = 0x01,
343  LPM2_AUTOSLEEP_DUR1 = 0x02,
344  LPM2_AUTOSLEEP_DUR2 = 0x04,
345  _LPM2_AUTOSLEEP_DUR_MASK = 7,
346  _LPM2_AUTOSLEEP_DUR_SHIFT = 0,
347 
348  LPM2_EXT_TRIG_SEL0 = 0x10,
349  LPM2_EXT_TRIG_SEL1 = 0x20,
350  _LPM2_EXT_TRIG_SEL_MASK = 3,
351  _LPM2_EXT_TRIG_SEL_SHIFT = 4,
352 
353  LPM2_POWER_SAVE_MODE = 0x40,
354  LPM2_FAST_POWERUP = 0x80
355  } LPM2_BITS_T;
356 
357 
361  typedef enum {
362  AUTOSLEEP_DUR_NONE = 0,
363  AUTOSLEEP_DUR_4MS = 1,
364  AUTOSLEEP_DUR_5MS = 2,
365  AUTOSLEEP_DUR_8MS = 3,
366  AUTOSLEEP_DUR_10MS = 4,
367  AUTOSLEEP_DUR_15MS = 5,
368  AUTOSLEEP_DUR_20MS = 6,
369  AUTOSLEEP_DUR_40MS = 7
370  } AUTOSLEEP_DUR_T;
371 
375  typedef enum {
376  EXT_TRIG_SEL_NONE = 0,
377  EXT_TRIG_SEL_INT1 = 1,
378  EXT_TRIG_SEL_INT2 = 2,
379  EXT_TRIG_SEL_SDO = 3 // if SPI3 mode (unsupported)
380  } EXT_TRIG_SEL_T;
381 
385  typedef enum {
386  _RATE_HBW_RESERVED_BITS = 0x0f | 0x10 | 0x20,
387 
388  RATE_HBW_SHADOW_DIS = 0x40,
389  RATE_HBW_DATA_HIGH_BW = 0x80
390  } RATE_HBW_BITS_T;
391 
395  typedef enum {
396  _INT_EN_0_RESERVED_BITS = 0x20 | 0x10 | 0x08 | 0x02 | 0x01,
397 
398  INT_EN_0_AUTO_OFFSET_EN = 0x04,
399 
400  INT_EN_0_FIFO_EN = 0x40,
401  INT_EN_0_DATA_EN = 0x80
402  } INT_EN_0_BITS_T;
403 
407  typedef enum {
408  _INT_EN_1_INT1_RESERVED_BITS = 0xf0,
409 
410  INT_EN_1_INT1_LVL = 0x01, // level or edge
411  INT_EN_1_INT1_OD = 0x02, // push-pull or open drain
412  INT_EN_1_INT2_LVL = 0x04,
413  INT_EN_1_INT2_OD = 0x08
414  } INT_EN_1_BITS_T;
415 
419  typedef enum {
420  _INT_MAP_0_RESERVED_BITS = 0xf0 | 0x04 | 0x01,
421 
422  INT_MAP_0_INT1_ANY = 0x02,
423  INT_MAP_0_INT1_HIGH = 0x08
425 
429  typedef enum {
430  INT_MAP_1_INT1_DATA = 0x01,
431  INT_MAP_1_INT1_FAST_OFFSET = 0x02,
432  INT_MAP_1_INT1_FIFO = 0x04,
433  INT_MAP_1_INT1_AUTO_OFFSET = 0x08,
434  INT_MAP_1_INT2_AUTO_OFFSET = 0x10,
435  INT_MAP_1_INT2_FIFO = 0x20,
436  INT_MAP_1_INT2_FAST_OFFSET = 0x40,
437  INT_MAP_1_INT2_DATA = 0x80
439 
443  typedef enum {
444  _INT_1A_RESERVED_BITS = 0xd5,
445 
446  INT_1A_ANY_UNFILT_DATA = 0x02,
447  INT_1A_HIGH_UNFILT_DATA = 0x08,
448  INT_1A_SLOW_OFFSET_UNFILT = 0x20
449  } INT_1A_BITS_T;
450 
454  typedef enum {
455  INT_1B_ANY_TH0 = 0x01,
456  INT_1B_ANY_TH1 = 0x02,
457  INT_1B_ANY_TH2 = 0x04,
458  INT_1B_ANY_TH3 = 0x08,
459  INT_1B_ANY_TH4 = 0x10,
460  INT_1B_ANY_TH5 = 0x20,
461  INT_1B_ANY_TH6 = 0x40,
462  _INT_1B_ANY_TH_MASK = 127,
463  _INT_1B_ANY_TH_SHIFT = 0,
464 
465  INT_1B_FAST_OFFSET_UNFILT = 0x80
466  } INT_1B_BITS_T;
467 
471  typedef enum {
472  _INT_1C_RESERVED_BITS = 0x08,
473 
474  INT_1C_ANY_EN_X = 0x01,
475  INT_1C_ANY_EN_Y = 0x02,
476  INT_1C_ANY_EN_Z = 0x04,
477 
478  INT_1C_ANY_DUR_SAMPLE0 = 0x10,
479  INT_1C_ANY_DUR_SAMPLE1 = 0x20,
480  INT_1C_ANY_DUR_SAMPLE_MASK = 3,
481  INT_1C_ANY_DUR_SAMPLE_SHIFT = 4,
482 
483  INT_1C_AWAKE_DUR0 = 0x40,
484  INT_1C_AWAKE_DUR1 = 0x80,
485  INT_1C_AWAKE_DUR_MASK = 3,
486  INT_1C_AWAKE_DUR_SHIFT = 6
487  } INT_1C_BITS_T;
488 
492  typedef enum {
493  ANY_DUR_SAMPLE_4 = 0, // samples
494  ANY_DUR_SAMPLE_8 = 1,
495  ANY_DUR_SAMPLE_12 = 2,
496  ANY_DUR_SAMPLE_16 = 3
498 
502  typedef enum {
503  AWAKE_DUR_SAMPLE_8 = 0, // samples
504  AWAKE_DUR_SAMPLE_16 = 1,
505  AWAKE_DUR_SAMPLE_32 = 2,
506  AWAKE_DUR_SAMPLE_64 = 3
508 
512  typedef enum {
513  _INT_1E_RESERVED_BITS = 0x7f,
514 
515  INT_1E_FIFO_WM_EN = 0x80
516  } INT_1E_BITS_T;
517 
521  typedef enum {
522  _INT_RST_LATCH_RESERVED_BITS = 0x20,
523 
524  INT_RST_LATCH0 = 0x01,
525  INT_RST_LATCH1 = 0x02,
526  INT_RST_LATCH2 = 0x04,
527  INT_RST_LATCH3 = 0x08,
528  _INT_RST_LATCH_MASK = 15,
529  _INT_RST_LATCH_SHIFT = 0,
530 
531  INT_RST_LATCH_STATUS_BIT = 0x10,
532 
533  INT_RST_LATCH_OFFSET_RESET = 0x40,
534  INT_RST_LATCH_RESET_INT = 0x80
536 
540  typedef enum {
541  RST_LATCH_NON_LATCHED = 0,
542  RST_LATCH_TEMPORARY_250MS = 1,
543  RST_LATCH_TEMPORARY_500MS = 2,
544  RST_LATCH_TEMPORARY_1S = 3,
545  RST_LATCH_TEMPORARY_2S = 4,
546  RST_LATCH_TEMPORARY_4S = 5,
547  RST_LATCH_TEMPORARY_8S = 6,
548  RST_LATCH_LATCHED = 7,
549 
550  // 8 == non latched
551 
552  RST_LATCH_TEMPORARY_250US = 9,
553  RST_LATCH_TEMPORARY_500US = 10,
554  RST_LATCH_TEMPORARY_1MS = 11,
555  RST_LATCH_TEMPORARY_12_5MS = 12,
556  RST_LATCH_TEMPORARY_25MS = 13,
557  RST_LATCH_TEMPORARY_50MS = 14
558 
559  // 15 == latched
560  } RST_LATCH_T;
561 
565  typedef enum {
566  HIGH_TH_EN = 0x01,
567 
568  HIGH_TH_TH0 = 0x02,
569  HIGH_TH_TH1 = 0x04,
570  HIGH_TH_TH2 = 0x08,
571  HIGH_TH_TH3 = 0x10,
572  HIGH_TH_TH4 = 0x20,
573  _HIGH_TH_TH_MASK = 31,
574  _HIGH_TH_TH_SHIFT = 1,
575 
576  HIGH_TH_HY0 = 0x40,
577  HIGH_TH_HY1 = 0x80,
578  _HIGH_TH_HY_MASK = 3,
579  _HIGH_TH_HY_SHIFT = 6
580  } HIGH_TH_BITS_T;
581 
585  typedef enum {
586  SOC_SLOW_OFFSET_EN_X = 0x01,
587  SOC_SLOW_OFFSET_EN_Y = 0x02,
588  SOC_SLOW_OFFSET_EN_Z = 0x04,
589 
590  SOC_SLOW_OFFSET_DUR0 = 0x08,
591  SOC_SLOW_OFFSET_DUR1 = 0x10,
592  SOC_SLOW_OFFSET_DUR2 = 0x20,
593  _SOC_SLOW_OFFSET_DUR_MASK = 7,
594  _SOC_SLOW_OFFSET_DUR_SHIFT = 3,
595 
596  SOC_SLOW_OFFSET_TH0 = 0x40,
597  SOC_SLOW_OFFSET_TH1 = 0x80,
598  _SOC_SLOW_OFFSET_TH_MASK = 3,
599  _SOC_SLOW_OFFSET_TH_SHIFT = 6
600  } SOC_BITS_T;
601 
605  typedef enum {
606  SLOW_OFFSET_DUR_40MS = 0, // 40ms
607  SLOW_OFFSET_DUR_80MS = 1,
608  SLOW_OFFSET_DUR_160MS = 2,
609  SLOW_OFFSET_DUR_320MS = 3,
610  SLOW_OFFSET_DUR_640MS = 4,
611  SLOW_OFFSET_DUR_1280MS = 5
613 
617  typedef enum {
618  SLOW_OFFSET_TH_0_1 = 0, // 0.1 degree/s
619  SLOW_OFFSET_TH_0_2 = 1,
620  SLOW_OFFSET_TH_0_5 = 2,
621  SLOW_OFFSET_TH_1 = 3
623 
627  typedef enum {
628  A_FOC_FAST_OFFSET_EN_X = 0x01,
629  A_FOC_FAST_OFFSET_EN_Y = 0x02,
630  A_FOC_FAST_OFFSET_EN_Z = 0x04,
631 
632  A_FOC_FAST_OFFSET_EN = 0x08,
633 
634  A_FOC_FAST_OFFSET_WORDLENGTH0 = 0x10,
635  A_FOC_FAST_OFFSET_WORDLENGTH1 = 0x20,
636  _A_FOC_FAST_OFFSET_WORDLENGTH_MASK = 3,
637  _A_FOC_FAST_OFFSET_WORDLENGTH_SHIFT = 4,
638 
639  A_FOC_AUTO_OFFSET_WORDLENGTH0 = 0x40,
640  A_FOC_AUTO_OFFSET_WORDLENGTH1 = 0x80,
641  _A_FOC_AUTO_OFFSET_WORDLENGTH_MASK = 3,
642  _A_FOC_AUTO_OFFSET_WORDLENGTH_SHIFT = 6
643  } A_FOC_BITS_T;
644 
648  typedef enum {
649  FAST_OFFSET_WORDLENGTH_32 = 0, // samples
650  FAST_OFFSET_WORDLENGTH_64 = 1,
651  FAST_OFFSET_WORDLENGTH_128 = 2,
652  FAST_OFFSET_WORDLENGTH_256 = 3
654 
658  typedef enum {
659  AUTO_OFFSET_WORDLENGTH_32 = 0, // samples
660  AUTO_OFFSET_WORDLENGTH_64 = 1,
661  AUTO_OFFSET_WORDLENGTH_128 = 2,
662  AUTO_OFFSET_WORDLENGTH_256 = 3
664 
668  typedef enum {
669  TRIM_NVM_CTRL_NVM_PROG_MODE = 0x01,
670  TRIM_NVM_CTRL_NVM_PROG_TRIG = 0x02,
671  TRIM_NVM_CTRL_NVM_PROG_RDY = 0x04,
672  TRIM_NVM_CTRL_NVM_PROG_LOAD = 0x08,
673 
674  TRIM_NVM_CTRL_NVM_REMAIN0 = 0x10,
675  TRIM_NVM_CTRL_NVM_REMAIN1 = 0x20,
676  TRIM_NVM_CTRL_NVM_REMAIN2 = 0x40,
677  TRIM_NVM_CTRL_NVM_REMAIN3 = 0x80,
678  _TRIM_NVM_CTRL_NVM_REMAIN_MASK = 15,
679  _TRIM_NVM_CTRL_NVM_REMAIN_SHIFT = 4
681 
685  typedef enum {
686  _SPI3_WDT_RESERVED_BITS = 0xf0 | 0x08,
687 
688  SPI3_WDT_SPI3 = 0x01, // 3-wire SPI - NOT SUPPORTED
689 
690  SPI3_WDT_I2C_WDT_SEL = 0x02,
691  SPI3_WDT_I2C_WDT_EN = 0x04
692 
693  // 0x08-0x80 reserved
694  } SPI3_WDT_BITS_T;
695 
699  typedef enum {
700  OFC1_OFFSET_Z0 = 0x01, // Z lsb (3:1)
701  OFC1_OFFSET_Z1 = 0x02,
702  OFC1_OFFSET_Z2 = 0x04,
703  _OFC1_OFFSET_Z_MASK = 7,
704  _OFC1_OFFSET_Z_SHIFT = 0,
705 
706  OFC1_OFFSET_Y0 = 0x08, // Y lsb (3:1)
707  OFC1_OFFSET_Y1 = 0x10,
708  OFC1_OFFSET_Y2 = 0x20,
709  _OFC1_OFFSET_Y_MASK = 7,
710  _OFC1_OFFSET_Y_SHIFT = 3,
711 
712  OFC1_OFFSET_X0 = 0x08, // bits 3:2 of X lsb. geez
713  OFC1_OFFSET_X1 = 0x10,
714  _OFC1_OFFSET_X_MASK = 3,
715  _OFC1_OFFSET_X_SHIFT = 6
717 
721  typedef enum {
722  GP0_OFFSET_Z = 0x01, // Z llsb (bit 0)
723  GP0_OFFSET_Y = 0x02, // Y llsb (bit 0)
724 
725  GP0_OFFSET_X0 = 0x04, // X llsbs (bits 1:0)
726  GP0_OFFSET_X1 = 0x08,
727  _GP0_OFFSET_X_MASK = 3,
728  _GP0_OFFSET_X_SHIFT = 2,
729 
730  GP0_GP00 = 0x10,
731  GP0_GP01 = 0x20,
732  GP0_GP02 = 0x40,
733  GP0_GP03 = 0x80,
734  _GP0_GP0_MASK = 15,
735  _GP0_GP0_SHIFT = 4
736  } GP0_BITS_T;
737 
741  typedef enum {
742  _BIST_RESERVED_BITS = 0x80 | 0x40 | 0x20 | 0x08,
743 
744  BIST_TRIG_BIST = 0x01,
745  BIST_BIST_RDY = 0x02,
746  BIST_BIST_FAIL = 0x04,
747 
748  BIST_RATE_OK = 0x10
749  } BIST_BITS_T;
750 
754  typedef enum {
755  FIFO_CONFIG_0_WATER_MARK0 = 0x01,
756  FIFO_CONFIG_0_WATER_MARK1 = 0x02,
757  FIFO_CONFIG_0_WATER_MARK2 = 0x04,
758  FIFO_CONFIG_0_WATER_MARK3 = 0x08,
759  FIFO_CONFIG_0_WATER_MARK4 = 0x10,
760  FIFO_CONFIG_0_WATER_MARK5 = 0x20,
761  FIFO_CONFIG_0_WATER_MARK6 = 0x40,
762  _FIFO_CONFIG_0_WATER_MARK_MASK = 127,
763  _FIFO_CONFIG_0_WATER_MARK_SHIFT = 0,
764 
765  FIFO_CONFIG_0_TAG = 0x80
767 
771  typedef enum {
772  _FIFO_CONFIG_1_RESERVED_BITS = 0x20 | 0x10 |0x08 | 0x04,
773 
774  FIFO_CONFIG_1_FIFO_DATA_SEL0 = 0x01,
775  FIFO_CONFIG_1_FIFO_DATA_SEL1 = 0x02,
776  _FIFO_CONFIG_1_FIFO_DATA_SEL = 3,
777  _FIFO_CONFIG_1_FIFO_DATA_SHIFT = 0,
778 
779  FIFO_CONFIG_1_FIFO_MODE0 = 0x40,
780  FIFO_CONFIG_1_FIFO_MODE1 = 0x80,
781  _FIFO_CONFIG_1_FIFO_MODE_MASK = 3,
782  _FIFO_CONFIG_1_FIFO_MODE_SHIFT = 6
784 
788  typedef enum {
789  FIFO_DATA_SEL_XYZ = 0,
790  FIFO_DATA_SEL_X = 1,
791  FIFO_DATA_SEL_Y = 2,
792  FIFO_DATA_SEL_Z = 3
793  } FIFO_DATA_SEL_T;
794 
798  typedef enum {
799  FIFO_MODE_BYPASS = 0,
800  FIFO_MODE_FIFO = 1,
801  FIFO_MODE_STREAM = 2
802  } FIFO_MODE_T;
803 
804  // interrupt selection for installISR() and uninstallISR()
805  typedef enum {
806  INTERRUPT_INT1,
807  INTERRUPT_INT2
808  } INTERRUPT_PINS_T;
809 
810 
827  BMG160(int bus=BMG160_I2C_BUS, int addr=BMG160_DEFAULT_ADDR,
828  int cs=-1);
829 
833  ~BMG160();
834 
838  void update();
839 
845  uint8_t getChipID();
846 
858  void getGyroscope(float *x, float *y, float *z);
859 
869  float *getGyroscope();
870 
880  float getTemperature(bool fahrenheit=false);
881 
894  void init(POWER_MODE_T pwr=POWER_MODE_NORMAL,
895  RANGE_T range=RANGE_250, BW_T bw=BW_400_47);
896 
903  void reset();
904 
911  void setRange(RANGE_T range);
912 
918  void setBandwidth(BW_T bw);
919 
928  void setPowerMode(POWER_MODE_T power);
929 
945  void enableFIFO(bool useFIFO);
946 
953  void fifoSetWatermark(int wm);
954 
962  void fifoConfig(FIFO_MODE_T mode, FIFO_DATA_SEL_T axes);
963 
971  uint8_t getInterruptEnable0();
972 
979  void setInterruptEnable0(uint8_t bits);
980 
988  uint8_t getInterruptMap0();
989 
997  void setInterruptMap0(uint8_t bits);
998 
1005  uint8_t getInterruptMap1();
1006 
1013  void setInterruptMap1(uint8_t bits);
1014 
1023  uint8_t getInterruptSrc();
1024 
1033  void setInterruptSrc(uint8_t bits);
1034 
1043  uint8_t getInterruptOutputControl();
1044 
1053  void setInterruptOutputControl(uint8_t bits);
1054 
1058  void clearInterruptLatches();
1059 
1067 
1075 
1083  uint8_t getInterruptStatus0();
1084 
1091  uint8_t getInterruptStatus1();
1092 
1099  uint8_t getInterruptStatus2();
1100 
1107  uint8_t getInterruptStatus3();
1108 
1120  void enableRegisterShadowing(bool shadow);
1121 
1130  void enableOutputFiltering(bool filter);
1131 
1132 #if defined(SWIGJAVA) || defined(JAVACALLBACK)
1133  void installISR(INTERRUPT_PINS_T intr, int gpio, mraa::Edge level,
1134  jobject runnable);
1135 #else
1136 
1148  void installISR(INTERRUPT_PINS_T intr, int gpio, mraa::Edge level,
1149  void (*isr)(void *), void *arg);
1150 #endif
1151 
1158  void uninstallISR(INTERRUPT_PINS_T intr);
1159 
1166  uint8_t readReg(uint8_t reg);
1167 
1175  int readRegs(uint8_t reg, uint8_t *buffer, int len);
1176 
1183  void writeReg(uint8_t reg, uint8_t val);
1184 
1185  protected:
1186  mraa::I2c *m_i2c;
1187  mraa::Spi *m_spi;
1188 
1189  mraa::Gpio *m_gpioIntr1;
1190  mraa::Gpio *m_gpioIntr2;
1191 
1192  // spi chip select
1193  mraa::Gpio *m_gpioCS;
1194 
1195  uint8_t m_addr;
1196 
1197  // SPI chip select
1198  void csOn();
1199  void csOff();
1200 
1201  // acc data
1202  float m_gyrX;
1203  float m_gyrY;
1204  float m_gyrZ;
1205 
1206  float m_gyrScale;
1207 
1208  float m_temperature;
1209 
1210  private:
1211  bool m_isSPI;
1212  // use the FIFO by default?
1213  bool m_useFIFO;
1214 
1215  // return a reference to a gpio pin pointer depending on intr
1216  mraa::Gpio*& getPin(INTERRUPT_PINS_T intr);
1217 
1218  // Adding a private function definition for java bindings
1219 #if defined(SWIGJAVA) || defined(JAVACALLBACK)
1220  void installISR(INTERRUPT_PINS_T intr, int gpio, mraa::Edge level,
1221  void (*isr)(void *), void *arg);
1222 #endif
1223  };
1224 }
void clearInterruptLatches()
Definition: bmg160.cxx:460
INT_MAP_1_BITS_T
Definition: bmg160.hpp:429
BIST_BITS_T
Definition: bmg160.hpp:741
BMG160_REGS_T
Definition: bmg160.hpp:83
INT_1C_BITS_T
Definition: bmg160.hpp:471
INT_EN_0_BITS_T
Definition: bmg160.hpp:395
HIGH_TH_BITS_T
Definition: bmg160.hpp:565
void setBandwidth(BW_T bw)
Definition: bmg160.cxx:369
uint8_t getInterruptStatus3()
Definition: bmg160.cxx:527
RATE_HBW_BITS_T
Definition: bmg160.hpp:385
void enableRegisterShadowing(bool shadow)
Definition: bmg160.cxx:488
float getTemperature(bool fahrenheit=false)
Definition: bmg160.cxx:324
RST_LATCH_T getInterruptLatchBehavior()
Definition: bmg160.cxx:469
LPM1_BITS_T
Definition: bmg160.hpp:293
POWER_MODE_T
Definition: bmg160.hpp:330
A_FOC_BITS_T
Definition: bmg160.hpp:627
float * getGyroscope()
Definition: bmg160.cxx:316
OFC1_OFFSET_BITS_T
Definition: bmg160.hpp:699
SLOW_OFFSET_TH_T
Definition: bmg160.hpp:617
uint8_t getInterruptStatus0()
Definition: bmg160.cxx:512
void setInterruptMap0(uint8_t bits)
Definition: bmg160.cxx:418
uint8_t readReg(uint8_t reg)
Definition: bmg160.cxx:203
uint8_t getInterruptOutputControl()
Definition: bmg160.cxx:448
GP0_BITS_T
Definition: bmg160.hpp:721
RST_LATCH_T
Definition: bmg160.hpp:540
uint8_t getChipID()
Definition: bmg160.cxx:299
BW_T
Definition: bmg160.hpp:279
API for the BMG160 16 bit Triaxial Gyroscope.
Definition: bmg160.hpp:70
FIFO_CONFIG_1_BITS_T
Definition: bmg160.hpp:771
void writeReg(uint8_t reg, uint8_t val)
Definition: bmg160.cxx:259
ANY_DUR_SAMPLE_T
Definition: bmg160.hpp:492
uint8_t getInterruptEnable0()
Definition: bmg160.cxx:401
SPI3_WDT_BITS_T
Definition: bmg160.hpp:685
INT_STATUS_0_BITS_T
Definition: bmg160.hpp:172
LPM2_BITS_T
Definition: bmg160.hpp:339
void setInterruptLatchBehavior(RST_LATCH_T latch)
Definition: bmg160.cxx:478
void installISR(INTERRUPT_PINS_T intr, int gpio, mraa::Edge level, void(*isr)(void *), void *arg)
Definition: bmg160.cxx:546
void uninstallISR(INTERRUPT_PINS_T intr)
Definition: bmg160.cxx:560
SLOW_OFFSET_DUR_T
Definition: bmg160.hpp:605
~BMG160()
Definition: bmg160.cxx:109
FIFO_MODE_T
Definition: bmg160.hpp:798
uint8_t getInterruptStatus1()
Definition: bmg160.cxx:517
uint8_t getInterruptStatus2()
Definition: bmg160.cxx:522
INT_1E_BITS_T
Definition: bmg160.hpp:512
INT_STATUS_3_BITS_T
Definition: bmg160.hpp:206
void setInterruptEnable0(uint8_t bits)
Definition: bmg160.cxx:406
void setInterruptSrc(uint8_t bits)
Definition: bmg160.cxx:441
void enableFIFO(bool useFIFO)
Definition: bmg160.cxx:198
SOC_BITS_T
Definition: bmg160.hpp:585
INT_EN_1_BITS_T
Definition: bmg160.hpp:407
FIFO_STATUS_BITS_T
Definition: bmg160.hpp:218
INT_STATUS_1_BITS_T
Definition: bmg160.hpp:182
AWAKE_DUR_SAMPLE_T
Definition: bmg160.hpp:502
INT_MAP_0_BITS_T
Definition: bmg160.hpp:419
void enableOutputFiltering(bool filter)
Definition: bmg160.cxx:500
void reset()
Definition: bmg160.cxx:332
INT_STATUS_2_BITS_T
Definition: bmg160.hpp:194
INT_1B_BITS_T
Definition: bmg160.hpp:454
BMG160(int bus=BMG160_I2C_BUS, int addr=BMG160_DEFAULT_ADDR, int cs=-1)
Definition: bmg160.cxx:45
void setPowerMode(POWER_MODE_T power)
Definition: bmg160.cxx:374
FIFO_DATA_SEL_T
Definition: bmg160.hpp:788
uint8_t getInterruptMap0()
Definition: bmg160.cxx:413
AUTOSLEEP_DUR_T
Definition: bmg160.hpp:361
uint8_t getInterruptMap1()
Definition: bmg160.cxx:425
FAST_OFFSET_WORDLENGTH_T
Definition: bmg160.hpp:648
void setRange(RANGE_T range)
Definition: bmg160.cxx:338
GYR_RANGE_BITS_T
Definition: bmg160.hpp:235
uint8_t getInterruptSrc()
Definition: bmg160.cxx:436
void update()
Definition: bmg160.cxx:145
AUTO_OFFSET_WORDLENGTH_T
Definition: bmg160.hpp:658
GYR_BW_BITS_T
Definition: bmg160.hpp:265
TRIM_NVM_CTRL_BITS_T
Definition: bmg160.hpp:668
SLEEP_DUR_T
Definition: bmg160.hpp:316
void init(POWER_MODE_T pwr=POWER_MODE_NORMAL, RANGE_T range=RANGE_250, BW_T bw=BW_400_47)
Definition: bmg160.cxx:122
FIFO_CONFIG_0_BITS_T
Definition: bmg160.hpp:754
RANGE_T
Definition: bmg160.hpp:254
void setInterruptOutputControl(uint8_t bits)
Definition: bmg160.cxx:453
void setInterruptMap1(uint8_t bits)
Definition: bmg160.cxx:430
int readRegs(uint8_t reg, uint8_t *buffer, int len)
Definition: bmg160.cxx:225
void fifoSetWatermark(int wm)
Definition: bmg160.cxx:385
EXT_TRIG_SEL_T
Definition: bmg160.hpp:375
INT_RST_LATCH_BITS_T
Definition: bmg160.hpp:521
void fifoConfig(FIFO_MODE_T mode, FIFO_DATA_SEL_T axes)
Definition: bmg160.cxx:393
INT_1A_BITS_T
Definition: bmg160.hpp:443