27 #include <mraa/i2c.hpp>
28 #include <mraa/spi.hpp>
29 #include <mraa/gpio.hpp>
31 #define BMG160_I2C_BUS 0
32 #define BMG160_SPI_BUS 0
33 #define BMG160_DEFAULT_ADDR 0x68
73 static const uint8_t BMG160_RESET_BYTE = 0xb6;
83 typedef enum : uint8_t {
88 REG_RATE_X_LSB = 0x02,
89 REG_RATE_X_MSB = 0x03,
90 REG_RATE_Y_LSB = 0x04,
91 REG_RATE_Y_MSB = 0x05,
92 REG_RATE_Z_LSB = 0x06,
93 REG_RATE_Z_MSB = 0x07,
97 REG_INT_STATUS_0 = 0x09,
98 REG_INT_STATUS_1 = 0x0a,
99 REG_INT_STATUS_2 = 0x0b,
100 REG_INT_STATUS_3 = 0x0c,
104 REG_FIFO_STATUS = 0x0e,
106 REG_GYR_RANGE = 0x0f,
113 REG_SOFTRESET = 0x14,
118 REG_INT_MAP_0 = 0x17,
119 REG_INT_MAP_1 = 0x18,
120 REG_INT_MAP_2 = 0x19,
132 REG_INT_RST_LATCH = 0x21,
134 REG_HIGH_TH_X = 0x22,
135 REG_HIGH_DUR_X = 0x23,
136 REG_HIGH_TH_Y = 0x24,
137 REG_HIGH_DUR_Y = 0x25,
138 REG_HIGH_TH_Z = 0x26,
139 REG_HIGH_DUR_Z = 0x27,
146 REG_TRIM_NVM_CTRL = 0x33,
162 REG_FIFO_CONFIG_0 = 0x3d,
163 REG_FIFO_CONFIG_1 = 0x3e,
173 _INT_STATUS_0_RESERVED_BITS = 0xf0 | 0x08 | 0x01,
175 INT_STATUS_0_HIGH_INT = 0x02,
176 INT_STATUS_0_ANY_INT = 0x04
183 _INT_STATUS_1_RESERVED_BITS = 0x0f,
185 INT_STATUS_1_FIFO_INT = 0x10,
186 INT_STATUS_1_FAST_OFFSET_INT = 0x20,
187 INT_STATUS_1_AUTO_OFFSET_INT = 0x40,
188 INT_STATUS_1_DATA_INT = 0x80
195 _INT_STATUS_2_RESERVED_BITS = 0xf0,
197 INT_STATUS_2_ANY_FIRST_X = 0x01,
198 INT_STATUS_2_ANY_FIRST_Y = 0x02,
199 INT_STATUS_2_ANY_FIRST_Z = 0x04,
200 INT_STATUS_2_ANY_SIGN = 0x08
207 _INT_STATUS_3_RESERVED_BITS = 0xf0,
209 INT_STATUS_3_HIGH_FIRST_X = 0x01,
210 INT_STATUS_3_HIGH_FIRST_Y = 0x02,
211 INT_STATUS_3_HIGH_FIRST_Z = 0x04,
212 INT_STATUS_3_HIGH_SIGN = 0x08
219 FIFO_STATUS_FRAME_COUNTER0 = 0x01,
220 FIFO_STATUS_FRAME_COUNTER1 = 0x02,
221 FIFO_STATUS_FRAME_COUNTER2 = 0x04,
222 FIFO_STATUS_FRAME_COUNTER3 = 0x08,
223 FIFO_STATUS_FRAME_COUNTER4 = 0x10,
224 FIFO_STATUS_FRAME_COUNTER5 = 0x20,
225 FIFO_STATUS_FRAME_COUNTER6 = 0x40,
226 _FIFO_STATUS_FRAME_COUNTER_MASK = 127,
227 _FIFO_STATUS_FRAME_COUNTER_SHIFT = 0,
229 FIFO_STATUS_FIFO_OVERRUN = 0x80
236 _GYR_RANGE_RESERVED_BITS = 0x20 | 0x10 | 0x08,
242 _GYR_RANGE_SHIFT = 0,
244 GYR_RANGE_FIXED0 = 0x40,
245 GYR_RANGE_FIXED1 = 0x80,
246 _GYR_RANGE_FIXED_MASK = 3,
247 _GYR_RANGE_FIXED_SHIFT = 6,
248 _GYR_RANGE_FIXED_VALUE = 2
266 _GYR_BW_RESERVED_BITS = 0xf0,
280 BW_2000_UNFILTERED = 0,
295 _LPM1_RESERVED_MASK = 0x40 | 0x10 | 0x01,
297 LPM1_SLEEP_DUR0 = 0x02,
298 LPM1_SLEEP_DUR1 = 0x04,
299 LPM1_SLEEP_DUR2 = 0x08,
300 _LPM1_SLEEP_MASK = 7,
301 _LPM1_SLEEP_SHIFT = 1,
306 LPM1_POWER_MODE0 = 0x20,
307 LPM1_POWER_MODE1 = 0x40,
308 LPM1_POWER_MODE2 = 0x80,
309 _LPM1_POWER_MODE_MASK = 7,
310 _LPM1_POWER_MODE_SHIFT = 5
331 POWER_MODE_NORMAL = 0,
332 POWER_MODE_DEEP_SUSPEND = 1,
333 POWER_MODE_SUSPEND = 4
340 _LPM2_RESERVED_BITS = 0x08,
342 LPM2_AUTOSLEEP_DUR0 = 0x01,
343 LPM2_AUTOSLEEP_DUR1 = 0x02,
344 LPM2_AUTOSLEEP_DUR2 = 0x04,
345 _LPM2_AUTOSLEEP_DUR_MASK = 7,
346 _LPM2_AUTOSLEEP_DUR_SHIFT = 0,
348 LPM2_EXT_TRIG_SEL0 = 0x10,
349 LPM2_EXT_TRIG_SEL1 = 0x20,
350 _LPM2_EXT_TRIG_SEL_MASK = 3,
351 _LPM2_EXT_TRIG_SEL_SHIFT = 4,
353 LPM2_POWER_SAVE_MODE = 0x40,
354 LPM2_FAST_POWERUP = 0x80
362 AUTOSLEEP_DUR_NONE = 0,
363 AUTOSLEEP_DUR_4MS = 1,
364 AUTOSLEEP_DUR_5MS = 2,
365 AUTOSLEEP_DUR_8MS = 3,
366 AUTOSLEEP_DUR_10MS = 4,
367 AUTOSLEEP_DUR_15MS = 5,
368 AUTOSLEEP_DUR_20MS = 6,
369 AUTOSLEEP_DUR_40MS = 7
376 EXT_TRIG_SEL_NONE = 0,
377 EXT_TRIG_SEL_INT1 = 1,
378 EXT_TRIG_SEL_INT2 = 2,
386 _RATE_HBW_RESERVED_BITS = 0x0f | 0x10 | 0x20,
388 RATE_HBW_SHADOW_DIS = 0x40,
389 RATE_HBW_DATA_HIGH_BW = 0x80
396 _INT_EN_0_RESERVED_BITS = 0x20 | 0x10 | 0x08 | 0x02 | 0x01,
398 INT_EN_0_AUTO_OFFSET_EN = 0x04,
400 INT_EN_0_FIFO_EN = 0x40,
401 INT_EN_0_DATA_EN = 0x80
408 _INT_EN_1_INT1_RESERVED_BITS = 0xf0,
410 INT_EN_1_INT1_LVL = 0x01,
411 INT_EN_1_INT1_OD = 0x02,
412 INT_EN_1_INT2_LVL = 0x04,
413 INT_EN_1_INT2_OD = 0x08
420 _INT_MAP_0_RESERVED_BITS = 0xf0 | 0x04 | 0x01,
422 INT_MAP_0_INT1_ANY = 0x02,
423 INT_MAP_0_INT1_HIGH = 0x08
430 INT_MAP_1_INT1_DATA = 0x01,
431 INT_MAP_1_INT1_FAST_OFFSET = 0x02,
432 INT_MAP_1_INT1_FIFO = 0x04,
433 INT_MAP_1_INT1_AUTO_OFFSET = 0x08,
434 INT_MAP_1_INT2_AUTO_OFFSET = 0x10,
435 INT_MAP_1_INT2_FIFO = 0x20,
436 INT_MAP_1_INT2_FAST_OFFSET = 0x40,
437 INT_MAP_1_INT2_DATA = 0x80
444 _INT_1A_RESERVED_BITS = 0xd5,
446 INT_1A_ANY_UNFILT_DATA = 0x02,
447 INT_1A_HIGH_UNFILT_DATA = 0x08,
448 INT_1A_SLOW_OFFSET_UNFILT = 0x20
455 INT_1B_ANY_TH0 = 0x01,
456 INT_1B_ANY_TH1 = 0x02,
457 INT_1B_ANY_TH2 = 0x04,
458 INT_1B_ANY_TH3 = 0x08,
459 INT_1B_ANY_TH4 = 0x10,
460 INT_1B_ANY_TH5 = 0x20,
461 INT_1B_ANY_TH6 = 0x40,
462 _INT_1B_ANY_TH_MASK = 127,
463 _INT_1B_ANY_TH_SHIFT = 0,
465 INT_1B_FAST_OFFSET_UNFILT = 0x80
472 _INT_1C_RESERVED_BITS = 0x08,
474 INT_1C_ANY_EN_X = 0x01,
475 INT_1C_ANY_EN_Y = 0x02,
476 INT_1C_ANY_EN_Z = 0x04,
478 INT_1C_ANY_DUR_SAMPLE0 = 0x10,
479 INT_1C_ANY_DUR_SAMPLE1 = 0x20,
480 INT_1C_ANY_DUR_SAMPLE_MASK = 3,
481 INT_1C_ANY_DUR_SAMPLE_SHIFT = 4,
483 INT_1C_AWAKE_DUR0 = 0x40,
484 INT_1C_AWAKE_DUR1 = 0x80,
485 INT_1C_AWAKE_DUR_MASK = 3,
486 INT_1C_AWAKE_DUR_SHIFT = 6
493 ANY_DUR_SAMPLE_4 = 0,
494 ANY_DUR_SAMPLE_8 = 1,
495 ANY_DUR_SAMPLE_12 = 2,
496 ANY_DUR_SAMPLE_16 = 3
503 AWAKE_DUR_SAMPLE_8 = 0,
504 AWAKE_DUR_SAMPLE_16 = 1,
505 AWAKE_DUR_SAMPLE_32 = 2,
506 AWAKE_DUR_SAMPLE_64 = 3
513 _INT_1E_RESERVED_BITS = 0x7f,
515 INT_1E_FIFO_WM_EN = 0x80
522 _INT_RST_LATCH_RESERVED_BITS = 0x20,
524 INT_RST_LATCH0 = 0x01,
525 INT_RST_LATCH1 = 0x02,
526 INT_RST_LATCH2 = 0x04,
527 INT_RST_LATCH3 = 0x08,
528 _INT_RST_LATCH_MASK = 15,
529 _INT_RST_LATCH_SHIFT = 0,
531 INT_RST_LATCH_STATUS_BIT = 0x10,
533 INT_RST_LATCH_OFFSET_RESET = 0x40,
534 INT_RST_LATCH_RESET_INT = 0x80
541 RST_LATCH_NON_LATCHED = 0,
542 RST_LATCH_TEMPORARY_250MS = 1,
543 RST_LATCH_TEMPORARY_500MS = 2,
544 RST_LATCH_TEMPORARY_1S = 3,
545 RST_LATCH_TEMPORARY_2S = 4,
546 RST_LATCH_TEMPORARY_4S = 5,
547 RST_LATCH_TEMPORARY_8S = 6,
548 RST_LATCH_LATCHED = 7,
552 RST_LATCH_TEMPORARY_250US = 9,
553 RST_LATCH_TEMPORARY_500US = 10,
554 RST_LATCH_TEMPORARY_1MS = 11,
555 RST_LATCH_TEMPORARY_12_5MS = 12,
556 RST_LATCH_TEMPORARY_25MS = 13,
557 RST_LATCH_TEMPORARY_50MS = 14
573 _HIGH_TH_TH_MASK = 31,
574 _HIGH_TH_TH_SHIFT = 1,
578 _HIGH_TH_HY_MASK = 3,
579 _HIGH_TH_HY_SHIFT = 6
586 SOC_SLOW_OFFSET_EN_X = 0x01,
587 SOC_SLOW_OFFSET_EN_Y = 0x02,
588 SOC_SLOW_OFFSET_EN_Z = 0x04,
590 SOC_SLOW_OFFSET_DUR0 = 0x08,
591 SOC_SLOW_OFFSET_DUR1 = 0x10,
592 SOC_SLOW_OFFSET_DUR2 = 0x20,
593 _SOC_SLOW_OFFSET_DUR_MASK = 7,
594 _SOC_SLOW_OFFSET_DUR_SHIFT = 3,
596 SOC_SLOW_OFFSET_TH0 = 0x40,
597 SOC_SLOW_OFFSET_TH1 = 0x80,
598 _SOC_SLOW_OFFSET_TH_MASK = 3,
599 _SOC_SLOW_OFFSET_TH_SHIFT = 6
606 SLOW_OFFSET_DUR_40MS = 0,
607 SLOW_OFFSET_DUR_80MS = 1,
608 SLOW_OFFSET_DUR_160MS = 2,
609 SLOW_OFFSET_DUR_320MS = 3,
610 SLOW_OFFSET_DUR_640MS = 4,
611 SLOW_OFFSET_DUR_1280MS = 5
618 SLOW_OFFSET_TH_0_1 = 0,
619 SLOW_OFFSET_TH_0_2 = 1,
620 SLOW_OFFSET_TH_0_5 = 2,
628 A_FOC_FAST_OFFSET_EN_X = 0x01,
629 A_FOC_FAST_OFFSET_EN_Y = 0x02,
630 A_FOC_FAST_OFFSET_EN_Z = 0x04,
632 A_FOC_FAST_OFFSET_EN = 0x08,
634 A_FOC_FAST_OFFSET_WORDLENGTH0 = 0x10,
635 A_FOC_FAST_OFFSET_WORDLENGTH1 = 0x20,
636 _A_FOC_FAST_OFFSET_WORDLENGTH_MASK = 3,
637 _A_FOC_FAST_OFFSET_WORDLENGTH_SHIFT = 4,
639 A_FOC_AUTO_OFFSET_WORDLENGTH0 = 0x40,
640 A_FOC_AUTO_OFFSET_WORDLENGTH1 = 0x80,
641 _A_FOC_AUTO_OFFSET_WORDLENGTH_MASK = 3,
642 _A_FOC_AUTO_OFFSET_WORDLENGTH_SHIFT = 6
649 FAST_OFFSET_WORDLENGTH_32 = 0,
650 FAST_OFFSET_WORDLENGTH_64 = 1,
651 FAST_OFFSET_WORDLENGTH_128 = 2,
652 FAST_OFFSET_WORDLENGTH_256 = 3
659 AUTO_OFFSET_WORDLENGTH_32 = 0,
660 AUTO_OFFSET_WORDLENGTH_64 = 1,
661 AUTO_OFFSET_WORDLENGTH_128 = 2,
662 AUTO_OFFSET_WORDLENGTH_256 = 3
669 TRIM_NVM_CTRL_NVM_PROG_MODE = 0x01,
670 TRIM_NVM_CTRL_NVM_PROG_TRIG = 0x02,
671 TRIM_NVM_CTRL_NVM_PROG_RDY = 0x04,
672 TRIM_NVM_CTRL_NVM_PROG_LOAD = 0x08,
674 TRIM_NVM_CTRL_NVM_REMAIN0 = 0x10,
675 TRIM_NVM_CTRL_NVM_REMAIN1 = 0x20,
676 TRIM_NVM_CTRL_NVM_REMAIN2 = 0x40,
677 TRIM_NVM_CTRL_NVM_REMAIN3 = 0x80,
678 _TRIM_NVM_CTRL_NVM_REMAIN_MASK = 15,
679 _TRIM_NVM_CTRL_NVM_REMAIN_SHIFT = 4
686 _SPI3_WDT_RESERVED_BITS = 0xf0 | 0x08,
688 SPI3_WDT_SPI3 = 0x01,
690 SPI3_WDT_I2C_WDT_SEL = 0x02,
691 SPI3_WDT_I2C_WDT_EN = 0x04
700 OFC1_OFFSET_Z0 = 0x01,
701 OFC1_OFFSET_Z1 = 0x02,
702 OFC1_OFFSET_Z2 = 0x04,
703 _OFC1_OFFSET_Z_MASK = 7,
704 _OFC1_OFFSET_Z_SHIFT = 0,
706 OFC1_OFFSET_Y0 = 0x08,
707 OFC1_OFFSET_Y1 = 0x10,
708 OFC1_OFFSET_Y2 = 0x20,
709 _OFC1_OFFSET_Y_MASK = 7,
710 _OFC1_OFFSET_Y_SHIFT = 3,
712 OFC1_OFFSET_X0 = 0x08,
713 OFC1_OFFSET_X1 = 0x10,
714 _OFC1_OFFSET_X_MASK = 3,
715 _OFC1_OFFSET_X_SHIFT = 6
725 GP0_OFFSET_X0 = 0x04,
726 GP0_OFFSET_X1 = 0x08,
727 _GP0_OFFSET_X_MASK = 3,
728 _GP0_OFFSET_X_SHIFT = 2,
742 _BIST_RESERVED_BITS = 0x80 | 0x40 | 0x20 | 0x08,
744 BIST_TRIG_BIST = 0x01,
745 BIST_BIST_RDY = 0x02,
746 BIST_BIST_FAIL = 0x04,
755 FIFO_CONFIG_0_WATER_MARK0 = 0x01,
756 FIFO_CONFIG_0_WATER_MARK1 = 0x02,
757 FIFO_CONFIG_0_WATER_MARK2 = 0x04,
758 FIFO_CONFIG_0_WATER_MARK3 = 0x08,
759 FIFO_CONFIG_0_WATER_MARK4 = 0x10,
760 FIFO_CONFIG_0_WATER_MARK5 = 0x20,
761 FIFO_CONFIG_0_WATER_MARK6 = 0x40,
762 _FIFO_CONFIG_0_WATER_MARK_MASK = 127,
763 _FIFO_CONFIG_0_WATER_MARK_SHIFT = 0,
765 FIFO_CONFIG_0_TAG = 0x80
772 _FIFO_CONFIG_1_RESERVED_BITS = 0x20 | 0x10 |0x08 | 0x04,
774 FIFO_CONFIG_1_FIFO_DATA_SEL0 = 0x01,
775 FIFO_CONFIG_1_FIFO_DATA_SEL1 = 0x02,
776 _FIFO_CONFIG_1_FIFO_DATA_SEL = 3,
777 _FIFO_CONFIG_1_FIFO_DATA_SHIFT = 0,
779 FIFO_CONFIG_1_FIFO_MODE0 = 0x40,
780 FIFO_CONFIG_1_FIFO_MODE1 = 0x80,
781 _FIFO_CONFIG_1_FIFO_MODE_MASK = 3,
782 _FIFO_CONFIG_1_FIFO_MODE_SHIFT = 6
789 FIFO_DATA_SEL_XYZ = 0,
799 FIFO_MODE_BYPASS = 0,
827 BMG160(
int bus=BMG160_I2C_BUS,
int addr=BMG160_DEFAULT_ADDR,
1132 #if defined(SWIGJAVA) || defined(JAVACALLBACK)
1133 void installISR(INTERRUPT_PINS_T intr,
int gpio, mraa::Edge level,
1148 void installISR(INTERRUPT_PINS_T intr,
int gpio, mraa::Edge level,
1149 void (*isr)(
void *),
void *arg);
1175 int readRegs(uint8_t reg, uint8_t *buffer,
int len);
1183 void writeReg(uint8_t reg, uint8_t val);
1189 mraa::Gpio *m_gpioIntr1;
1190 mraa::Gpio *m_gpioIntr2;
1193 mraa::Gpio *m_gpioCS;
1208 float m_temperature;
1216 mraa::Gpio*& getPin(INTERRUPT_PINS_T intr);
1219 #if defined(SWIGJAVA) || defined(JAVACALLBACK)
1220 void installISR(INTERRUPT_PINS_T intr,
int gpio, mraa::Edge level,
1221 void (*isr)(
void *),
void *arg);
void clearInterruptLatches()
Definition: bmg160.cxx:460
INT_MAP_1_BITS_T
Definition: bmg160.hpp:429
BIST_BITS_T
Definition: bmg160.hpp:741
BMG160_REGS_T
Definition: bmg160.hpp:83
INT_1C_BITS_T
Definition: bmg160.hpp:471
INT_EN_0_BITS_T
Definition: bmg160.hpp:395
HIGH_TH_BITS_T
Definition: bmg160.hpp:565
void setBandwidth(BW_T bw)
Definition: bmg160.cxx:369
uint8_t getInterruptStatus3()
Definition: bmg160.cxx:527
RATE_HBW_BITS_T
Definition: bmg160.hpp:385
void enableRegisterShadowing(bool shadow)
Definition: bmg160.cxx:488
float getTemperature(bool fahrenheit=false)
Definition: bmg160.cxx:324
RST_LATCH_T getInterruptLatchBehavior()
Definition: bmg160.cxx:469
LPM1_BITS_T
Definition: bmg160.hpp:293
POWER_MODE_T
Definition: bmg160.hpp:330
A_FOC_BITS_T
Definition: bmg160.hpp:627
float * getGyroscope()
Definition: bmg160.cxx:316
OFC1_OFFSET_BITS_T
Definition: bmg160.hpp:699
SLOW_OFFSET_TH_T
Definition: bmg160.hpp:617
uint8_t getInterruptStatus0()
Definition: bmg160.cxx:512
void setInterruptMap0(uint8_t bits)
Definition: bmg160.cxx:418
uint8_t readReg(uint8_t reg)
Definition: bmg160.cxx:203
uint8_t getInterruptOutputControl()
Definition: bmg160.cxx:448
GP0_BITS_T
Definition: bmg160.hpp:721
RST_LATCH_T
Definition: bmg160.hpp:540
uint8_t getChipID()
Definition: bmg160.cxx:299
BW_T
Definition: bmg160.hpp:279
API for the BMG160 16 bit Triaxial Gyroscope.
Definition: bmg160.hpp:70
FIFO_CONFIG_1_BITS_T
Definition: bmg160.hpp:771
void writeReg(uint8_t reg, uint8_t val)
Definition: bmg160.cxx:259
ANY_DUR_SAMPLE_T
Definition: bmg160.hpp:492
uint8_t getInterruptEnable0()
Definition: bmg160.cxx:401
SPI3_WDT_BITS_T
Definition: bmg160.hpp:685
INT_STATUS_0_BITS_T
Definition: bmg160.hpp:172
LPM2_BITS_T
Definition: bmg160.hpp:339
void setInterruptLatchBehavior(RST_LATCH_T latch)
Definition: bmg160.cxx:478
void installISR(INTERRUPT_PINS_T intr, int gpio, mraa::Edge level, void(*isr)(void *), void *arg)
Definition: bmg160.cxx:546
void uninstallISR(INTERRUPT_PINS_T intr)
Definition: bmg160.cxx:560
SLOW_OFFSET_DUR_T
Definition: bmg160.hpp:605
~BMG160()
Definition: bmg160.cxx:109
FIFO_MODE_T
Definition: bmg160.hpp:798
uint8_t getInterruptStatus1()
Definition: bmg160.cxx:517
uint8_t getInterruptStatus2()
Definition: bmg160.cxx:522
INT_1E_BITS_T
Definition: bmg160.hpp:512
INT_STATUS_3_BITS_T
Definition: bmg160.hpp:206
void setInterruptEnable0(uint8_t bits)
Definition: bmg160.cxx:406
void setInterruptSrc(uint8_t bits)
Definition: bmg160.cxx:441
void enableFIFO(bool useFIFO)
Definition: bmg160.cxx:198
SOC_BITS_T
Definition: bmg160.hpp:585
INT_EN_1_BITS_T
Definition: bmg160.hpp:407
FIFO_STATUS_BITS_T
Definition: bmg160.hpp:218
INT_STATUS_1_BITS_T
Definition: bmg160.hpp:182
AWAKE_DUR_SAMPLE_T
Definition: bmg160.hpp:502
INT_MAP_0_BITS_T
Definition: bmg160.hpp:419
void enableOutputFiltering(bool filter)
Definition: bmg160.cxx:500
void reset()
Definition: bmg160.cxx:332
INT_STATUS_2_BITS_T
Definition: bmg160.hpp:194
INT_1B_BITS_T
Definition: bmg160.hpp:454
BMG160(int bus=BMG160_I2C_BUS, int addr=BMG160_DEFAULT_ADDR, int cs=-1)
Definition: bmg160.cxx:45
void setPowerMode(POWER_MODE_T power)
Definition: bmg160.cxx:374
FIFO_DATA_SEL_T
Definition: bmg160.hpp:788
uint8_t getInterruptMap0()
Definition: bmg160.cxx:413
AUTOSLEEP_DUR_T
Definition: bmg160.hpp:361
uint8_t getInterruptMap1()
Definition: bmg160.cxx:425
FAST_OFFSET_WORDLENGTH_T
Definition: bmg160.hpp:648
void setRange(RANGE_T range)
Definition: bmg160.cxx:338
GYR_RANGE_BITS_T
Definition: bmg160.hpp:235
uint8_t getInterruptSrc()
Definition: bmg160.cxx:436
void update()
Definition: bmg160.cxx:145
AUTO_OFFSET_WORDLENGTH_T
Definition: bmg160.hpp:658
GYR_BW_BITS_T
Definition: bmg160.hpp:265
TRIM_NVM_CTRL_BITS_T
Definition: bmg160.hpp:668
SLEEP_DUR_T
Definition: bmg160.hpp:316
void init(POWER_MODE_T pwr=POWER_MODE_NORMAL, RANGE_T range=RANGE_250, BW_T bw=BW_400_47)
Definition: bmg160.cxx:122
FIFO_CONFIG_0_BITS_T
Definition: bmg160.hpp:754
RANGE_T
Definition: bmg160.hpp:254
void setInterruptOutputControl(uint8_t bits)
Definition: bmg160.cxx:453
void setInterruptMap1(uint8_t bits)
Definition: bmg160.cxx:430
int readRegs(uint8_t reg, uint8_t *buffer, int len)
Definition: bmg160.cxx:225
void fifoSetWatermark(int wm)
Definition: bmg160.cxx:385
EXT_TRIG_SEL_T
Definition: bmg160.hpp:375
INT_RST_LATCH_BITS_T
Definition: bmg160.hpp:521
void fifoConfig(FIFO_MODE_T mode, FIFO_DATA_SEL_T axes)
Definition: bmg160.cxx:393
INT_1A_BITS_T
Definition: bmg160.hpp:443