upm  1.3.0
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bma250e_defs.h
1 /*
2  * Author: Jon Trulson <jtrulson@ics.com>
3  * Copyright (c) 2017 Intel Corporation.
4  *
5  * The MIT License
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining
8  * a copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sublicense, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be
16  * included in all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
21  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26 #pragma once
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 #define BMA250E_DEFAULT_I2C_BUS 0
33 #define BMA250E_DEFAULT_SPI_BUS 0
34 #define BMA250E_DEFAULT_ADDR 0x18
35 
36 // special reset byte
37 #define BMA250E_RESET_BYTE 0xb6
38 
39  // NOTE: Reserved registers must not be written into. Reading
40  // from them may return indeterminate values. Registers
41  // containing reserved bitfields must be written as 0. Reading
42  // reserved bitfields may return indeterminate values.
43 
47  typedef enum {
48  BMA250E_REG_CHIP_ID = 0x00,
49 
50  // 0x01 reserved
51 
52  BMA250E_REG_ACCD_X_LSB = 0x02,
53  BMA250E_REG_ACCD_X_MSB = 0x03,
54  BMA250E_REG_ACCD_Y_LSB = 0x04,
55  BMA250E_REG_ACCD_Y_MSB = 0x05,
56  BMA250E_REG_ACCD_Z_LSB = 0x06,
57  BMA250E_REG_ACCD_Z_MSB = 0x07,
58 
59  BMA250E_REG_TEMP = 0x08,
60 
61  BMA250E_REG_INT_STATUS_0 = 0x09,
62  BMA250E_REG_INT_STATUS_1 = 0x0a,
63  BMA250E_REG_INT_STATUS_2 = 0x0b,
64  BMA250E_REG_INT_STATUS_3 = 0x0c,
65 
66  // 0x0d reserved
67 
68  BMA250E_REG_FIFO_STATUS = 0x0e,
69 
70  BMA250E_REG_PMU_RANGE = 0x0f,
71  BMA250E_REG_PMU_BW = 0x10,
72  BMA250E_REG_PMU_LPW = 0x11,
73  BMA250E_REG_PMU_LOW_POWER = 0x12,
74 
75  BMA250E_REG_ACC_HBW = 0x13,
76 
77  BMA250E_REG_SOFTRESET = 0x14,
78 
79  // 0x15 reserved
80 
81  BMA250E_REG_INT_EN_0 = 0x16,
82  BMA250E_REG_INT_EN_1 = 0x17,
83  BMA250E_REG_INT_EN_2 = 0x18,
84 
85  BMA250E_REG_INT_MAP_0 = 0x19,
86  BMA250E_REG_INT_MAP_1 = 0x1a,
87  BMA250E_REG_INT_MAP_2 = 0x1b,
88 
89  // 0x1c-0x1d reserved
90 
91  BMA250E_REG_INT_SRC = 0x1e,
92 
93  // 0x1f reserved
94 
95  BMA250E_REG_INT_OUT_CTRL = 0x20,
96  BMA250E_REG_INT_RST_LATCH = 0x21,
97 
98  BMA250E_REG_INT_0 = 0x22,
99  BMA250E_REG_INT_1 = 0x23,
100  BMA250E_REG_INT_2 = 0x24,
101  BMA250E_REG_INT_3 = 0x25,
102  BMA250E_REG_INT_4 = 0x26,
103  BMA250E_REG_INT_5 = 0x27,
104  BMA250E_REG_INT_6 = 0x28,
105  BMA250E_REG_INT_7 = 0x29,
106  BMA250E_REG_INT_8 = 0x2a,
107  BMA250E_REG_INT_9 = 0x2b,
108  BMA250E_REG_INT_A = 0x2c,
109  BMA250E_REG_INT_B = 0x2d,
110  BMA250E_REG_INT_C = 0x2e,
111  BMA250E_REG_INT_D = 0x2f,
112 
113  BMA250E_REG_FIFO_CONFIG_0 = 0x30,
114 
115  // 0x31 reserved
116 
117  BMA250E_REG_PMU_SELFTEST = 0x32,
118 
119  BMA250E_REG_TRIM_NVM_CTRL = 0x33,
120 
121  BMA250E_REG_SPI3_WDT = 0x34,
122 
123  // 0x35 reserved
124 
125  BMA250E_REG_OFC_CTRL = 0x36,
126  BMA250E_REG_OFC_SETTING = 0x37,
127 
128  BMA250E_REG_OFC_OFFSET_X = 0x38,
129  BMA250E_REG_OFC_OFFSET_Y = 0x39,
130  BMA250E_REG_OFC_OFFSET_Z = 0x3a,
131 
132  BMA250E_REG_TRIM_GP0 = 0x3b,
133  BMA250E_REG_TRIM_GP1 = 0x3c,
134 
135  // 0x3d reserved
136 
137  BMA250E_REG_FIFO_CONFIG_1 = 0x3e,
138  BMA250E_REG_FIFO_DATA = 0x3f
139 
140  } BMA250E_REGS_T;
141 
146  typedef enum {
147  BMA250E_ACCD10_LSB_NEW_DATA = 0x01, // data
148  // updated
149  // since last
150  // read
151 
152  // 0x02-0x20 reserved
153 
154  BMA250E_ACCD10_LSB0 = 0x40, // lower 2
155  // bits of
156  // LSB data
157  BMA250E_ACCD10_LSB1 = 0x80,
158  _BMA250E_ACCD10_LSB_MASK = 3,
159  _BMA250E_ACCD10_LSB_SHIFT = 6
160  } BMA250E_ACCD10_LSB_BITS_T;
161 
166  typedef enum {
167  BMA250E_ACCD12_LSB_NEW_DATA = 0x01, // data
168  // updated
169  // since last
170  // read
171 
172  // 0x02-0x08 reserved
173 
174  BMA250E_ACCD12_LSB0 = 0x10, // lower 4
175  // bits of
176  // LSB data
177  BMA250E_ACCD12_LSB1 = 0x20,
178  BMA250E_ACCD12_LSB2 = 0x40,
179  BMA250E_ACCD12_LSB3 = 0x80,
180  _BMA250E_ACCD12_LSB_MASK = 15,
181  _BMA250E_ACCD12_LSB_SHIFT = 4
182  } BMA250E_ACCD12_LSB_BITS_T;
183 
187  typedef enum {
188  BMA250E_INT_STATUS_0_LOW = 0x01,
189  BMA250E_INT_STATUS_0_HIGH = 0x02,
190  BMA250E_INT_STATUS_0_SLOPE = 0x04,
191  BMA250E_INT_STATUS_0_SLO_NOT_MOT = 0x08,
192  BMA250E_INT_STATUS_0_D_TAP = 0x10,
193  BMA250E_INT_STATUS_0_S_TAP = 0x20,
194  BMA250E_INT_STATUS_0_ORIENT = 0x40,
195  BMA250E_INT_STATUS_0_FLAT = 0x80
196  } BMA250E_INT_STATUS_0_BITS_T;
197 
201  typedef enum {
202  _BMA250E_INT_STATUS_1_RESERVED_BITS = 0x0f | 0x10,
203  // 0x01-0x10 reserved
204  BMA250E_INT_STATUS_1_FIFO_FULL = 0x20,
205  BMA250E_INT_STATUS_1_FIFO_WM = 0x40,
206  BMA250E_INT_STATUS_1_DATA = 0x80 // data ready int
207  } BMA250E_INT_STATUS_1_BITS_T;
208 
212  typedef enum {
213  BMA250E_INT_STATUS_2_SLOPE_FIRST_X = 0x01,
214  BMA250E_INT_STATUS_2_SLOPE_FIRST_Y = 0x02,
215  BMA250E_INT_STATUS_2_SLOPE_FIRST_Z = 0x04,
216  BMA250E_INT_STATUS_2_SLOPE_SIGN = 0x08,
217  BMA250E_INT_STATUS_2_TAP_FIRST_X = 0x10,
218  BMA250E_INT_STATUS_2_TAP_FIRST_Y = 0x20,
219  BMA250E_INT_STATUS_2_TAP_FIRST_Z = 0x40,
220  BMA250E_INT_STATUS_2_TAP_SIGN = 0x80
221  } BMA250E_INT_STATUS_2_BITS_T;
222 
226  typedef enum {
227  BMA250E_INT_STATUS_3_HIGH_FIRST_X = 0x01,
228  BMA250E_INT_STATUS_3_HIGH_FIRST_Y = 0x02,
229  BMA250E_INT_STATUS_3_HIGH_FIRST_Z = 0x04,
230  BMA250E_INT_STATUS_3_HIGH_SIGN = 0x08,
231 
232  BMA250E_INT_STATUS_3_ORIENT0 = 0x10,
233  BMA250E_INT_STATUS_3_ORIENT1 = 0x20,
234  BMA250E_INT_STATUS_3_ORIENT2 = 0x40,
235  _BMA250E_INT_STATUS_3_ORIENT_MASK = 7,
236  _BMA250E_INT_STATUS_3_ORIENT_SHIFT = 4,
237 
238  BMA250E_INT_STATUS_3_FLAT = 0x80
239  } INT_STATUS_3_BITS_T;
240 
244  typedef enum {
245  BMA250E_ORIENT_POTRAIT_UPRIGHT = 0,
246  BMA250E_ORIENT_POTRAIT_UPSIDE_DOWN = 1,
247  BMA250E_ORIENT_LANDSCAPE_LEFT = 2,
248  BMA250E_ORIENT_LANDSCAPE_RIGHT = 3,
249  } BMA250E_ORIENT_T;
250 
254  typedef enum {
255  BMA250E_FIFO_STATUS_FRAME_COUNTER0 = 0x01,
256  BMA250E_FIFO_STATUS_FRAME_COUNTER1 = 0x02,
257  BMA250E_FIFO_STATUS_FRAME_COUNTER2 = 0x04,
258  BMA250E_FIFO_STATUS_FRAME_COUNTER3 = 0x08,
259  BMA250E_FIFO_STATUS_FRAME_COUNTER4 = 0x10,
260  BMA250E_FIFO_STATUS_FRAME_COUNTER5 = 0x20,
261  BMA250E_FIFO_STATUS_FRAME_COUNTER6 = 0x40,
262  _BMA250E_FIFO_STATUS_FRAME_COUNTER_MASK = 127,
263  _BMA250E_FIFO_STATUS_FRAME_COUNTER_SHIFT = 0,
264 
265  BMA250E_FIFO_STATUS_FIFO_OVERRUN = 0x80
266  } BMA250E_FIFO_STATUS_BITS_T;
267 
271  typedef enum {
272  BMA250E_PMU_RANGE0 = 0x01,
273  BMA250E_PMU_RANGE1 = 0x02,
274  BMA250E_PMU_RANGE2 = 0x04,
275  BMA250E_PMU_RANGE3 = 0x08,
276  _BMA250E_PMU_RANGE_MASK = 15,
277  _BMA250E_PMU_RANGE_SHIFT = 0
278 
279  // 0x10-0x80 reserved
280  } BMA250E_PMU_RANGE_BITS_T;
281 
285  typedef enum {
286  BMA250E_RANGE_2G = 3,
287  BMA250E_RANGE_4G = 5,
288  BMA250E_RANGE_8G = 8,
289  BMA250E_RANGE_16G = 12
290  } BMA250E_RANGE_T;
291 
295  typedef enum {
296  BMA250E_PMU_BW0 = 0x01,
297  BMA250E_PMU_BW1 = 0x02,
298  BMA250E_PMU_BW2 = 0x04,
299  BMA250E_PMU_BW3 = 0x08,
300  BMA250E_PMU_BW4 = 0x10,
301  _BMA250E_PMU_BW_MASK = 31,
302  _BMA250E_PMU_BW_SHIFT = 0
303 
304  // 0x20-0x80 reserved
305  } BMA250E_PMU_BW_BITS_T;
306 
310  typedef enum {
311  BMA250E_BW_7_81 = 8, // 7.81 Hz
312  BMA250E_BW_15_63 = 9,
313  BMA250E_BW_31_25 = 10,
314  BMA250E_BW_62_5 = 11,
315  BMA250E_BW_125 = 12,
316  BMA250E_BW_250 = 13,
317  BMA250E_BW_500 = 14,
318  BMA250E_BW_1000 = 15
319  } BMA250E_BW_T;
320 
324  typedef enum {
325  // 0x01 reserved
326  _BMA250E_PMU_LPW_RESERVED_MASK = 0x01,
327 
328  BMA250E_PMU_LPW_SLEEP_DUR0 = 0x02, // sleep dur
329  // in low
330  // power mode
331  BMA250E_PMU_LPW_SLEEP_DUR1 = 0x04,
332  BMA250E_PMU_LPW_SLEEP_DUR2 = 0x08,
333  BMA250E_PMU_LPW_SLEEP_DUR3 = 0x10,
334  _BMA250E_PMU_LPW_SLEEP_MASK = 15,
335  _BMA250E_PMU_LPW_SLEEP_SHIFT = 1,
336 
337  // These are separate bits, deep_suspend, lowpower_en and
338  // suspend (and if all 0, normal). Since only specific
339  // combinations are allowed, we will treat this as a 3 bit
340  // bitfield called POWER_MODE.
341  BMA250E_PMU_LPW_POWER_MODE0 = 0x20, // deep_suspend
342  BMA250E_PMU_LPW_POWER_MODE1 = 0x40, // lowpower_en
343  BMA250E_PMU_LPW_POWER_MODE2 = 0x80, // suspend
344  _BMA250E_PMU_LPW_POWER_MODE_MASK = 7,
345  _BMA250E_PMU_LPW_POWER_MODE_SHIFT = 5
346  } BMA250E_PMU_LPW_BITS_T;
347 
351  typedef enum {
352  BMA250E_SLEEP_DUR_0_5 = 0, // 0.5ms
353  BMA250E_SLEEP_DUR_1 = 6,
354  BMA250E_SLEEP_DUR_2 = 7,
355  BMA250E_SLEEP_DUR_4 = 8,
356  BMA250E_SLEEP_DUR_6 = 9,
357  BMA250E_SLEEP_DUR_10 = 10,
358  BMA250E_SLEEP_DUR_25 = 11,
359  BMA250E_SLEEP_DUR_50 = 12,
360  BMA250E_SLEEP_DUR_100 = 13,
361  BMA250E_SLEEP_DUR_500 = 14,
362  BMA250E_SLEEP_DUR_1000 = 15
363  } BMA250E_SLEEP_DUR_T;
364 
368  typedef enum {
369  BMA250E_POWER_MODE_NORMAL = 0,
370  BMA250E_POWER_MODE_DEEP_SUSPEND = 1,
371  BMA250E_POWER_MODE_LOW_POWER = 2,
372  BMA250E_POWER_MODE_SUSPEND = 4
373  } BMA250E_POWER_MODE_T;
374 
378  typedef enum {
379  _BMA250E_LOW_POWER_RESERVED_BITS = 0x0f | 0x10 | 0x80,
380 
381  // 0x01-0x10 reserved
382  BMA250E_LOW_POWER_SLEEPTIMER_MODE = 0x20,
383  BMA250E_LOW_POWER_LOWPOWER_MODE = 0x40 // LPM1 or
384  // LPM2
385  // mode. see
386  // DS.
387  // 0x80 reserved
388  } BMA250E_LOW_POWER_BITS_T;
389 
393  typedef enum {
394  _BMA250E_ACC_HBW_RESERVED_BITS = 0x0f | 0x10 | 0x20,
395 
396  // 0x01-0x20 reserved
397  BMA250E_ACC_HBW_SHADOW_DIS = 0x40,
398  BMA250E_ACC_HBW_DATA_HIGH_BW = 0x80
399  } BMA250E_ACC_HBW_BITS_T;
400 
404  typedef enum {
405  _BMA250E_INT_EN_0_RESERVED_BITS = 0x08,
406 
407  BMA250E_INT_EN_0_SLOPE_EN_X = 0x01,
408  BMA250E_INT_EN_0_SLOPE_EN_Y = 0x02,
409  BMA250E_INT_EN_0_SLOPE_EN_Z = 0x04,
410 
411  // 0x08 reserved
412 
413  BMA250E_INT_EN_0_D_TAP_EN = 0x10,
414  BMA250E_INT_EN_0_S_TAP_EN = 0x20,
415  BMA250E_INT_EN_0_ORIENT_EN = 0x40,
416  BMA250E_INT_EN_0_FLAT_EN = 0x80
417  } BMA250E_INT_EN_0_BITS_T;
418 
422  typedef enum {
423  _BMA250E_INT_EN_1_RESERVED_BITS = 0x80,
424 
425  BMA250E_INT_EN_1_HIGH_EN_X = 0x01,
426  BMA250E_INT_EN_1_HIGH_EN_Y = 0x02,
427  BMA250E_INT_EN_1_HIGH_EN_Z = 0x04,
428  BMA250E_INT_EN_1_LOW_EN = 0x08,
429  BMA250E_INT_EN_1_DATA_EN = 0x10,
430  BMA250E_INT_EN_1_INT_FFULL_EN = 0x20, // fifo full
431  BMA250E_INT_EN_1_INT_FWM_EN = 0x40 // fifo watermark
432 
433  // 0x80 reserved
434  } BMA250E_INT_EN_1_BITS_T;
435 
439  typedef enum {
440  _BMA250E_INT_EN_2_RESERVED_BITS = 0xf0,
441 
442  BMA250E_INT_EN_2_SLO_NO_MOT_EN_X = 0x01,
443  BMA250E_INT_EN_2_SLO_NO_MOT_EN_Y = 0x02,
444  BMA250E_INT_EN_2_SLO_NO_MOT_EN_Z = 0x04,
445  BMA250E_INT_EN_2_SLO_NO_MOT_SEL = 0x08
446 
447  // 0x10-0x80 reserved
448  } BMA250E_INT_EN_2_BITS_T;
449 
453  typedef enum {
454  BMA250E_INT_MAP_0_INT1_LOW = 0x01,
455  BMA250E_INT_MAP_0_INT1_HIGH = 0x02,
456  BMA250E_INT_MAP_0_INT1_SLOPE = 0x04,
457  BMA250E_INT_MAP_0_INT1_SLO_NO_MOT = 0x08,
458  BMA250E_INT_MAP_0_INT1_D_TAP = 0x10,
459  BMA250E_INT_MAP_0_INT1_S_TAP = 0x20,
460  BMA250E_INT_MAP_0_INT1_ORIENT = 0x40,
461  BMA250E_INT_MAP_0_INT1_FLAT = 0x80
462  } BMA250E_INT_MAP_0_BITS_T;
463 
467  typedef enum {
468  _BMA250E_INT_MAP_1_INT1_RESERVED_BITS = 0x08 | 0x10,
469 
470  BMA250E_INT_MAP_1_INT1_DATA = 0x01,
471  BMA250E_INT_MAP_1_INT1_FWM = 0x02,
472  BMA250E_INT_MAP_1_INT1_FFULL = 0x04,
473 
474  // 0x08-0x10 reserved
475 
476  BMA250E_INT_MAP_1_INT2_FFULL = 0x20,
477  BMA250E_INT_MAP_1_INT2_FWM = 0x40,
478  BMA250E_INT_MAP_1_INT2_DATA = 0x80
479  } BMA250E_INT_MAP_1_BITS_T;
480 
484  typedef enum {
485  BMA250E_INT_MAP_2_INT2_LOW = 0x01,
486  BMA250E_INT_MAP_2_INT2_HIGH = 0x02,
487  BMA250E_INT_MAP_2_INT2_SLOPE = 0x04,
488  BMA250E_INT_MAP_2_INT2_SLO_NO_MOT = 0x08,
489  BMA250E_INT_MAP_2_INT2_D_TAP = 0x10,
490  BMA250E_INT_MAP_2_INT2_S_TAP = 0x20,
491  BMA250E_INT_MAP_2_INT2_ORIENT = 0x40,
492  BMA250E_INT_MAP_2_INT2_FLAT = 0x80
493  } BMA250E_INT_MAP_2_BITS_T;
494 
498  typedef enum {
499  _BMA250E_INT_SRC_RESERVED_BITS = 0x40 | 0x80,
500 
501  BMA250E_INT_SRC_LOW = 0x01,
502  BMA250E_INT_SRC_HIGH = 0x02,
503  BMA250E_INT_SRC_SLO_NO_MOT = 0x04,
504  BMA250E_INT_SRC_SLOPE = 0x08,
505  BMA250E_INT_SRC_TAP = 0x10,
506  BMA250E_INT_SRC_DATA = 0x20
507 
508  // 0x40-0x80 reserved
509  } BMA250E_INT_SRC_BITS_T;
510 
514  typedef enum {
515  _BMA250E_INT_OUT_CTRL_INT1_RESERVED_BITS = 0xf0,
516 
517  BMA250E_INT_OUT_CTRL_INT1_LVL = 0x01, // level or edge
518  BMA250E_INT_OUT_CTRL_INT1_OD = 0x02, // push-pull
519  // or open
520  // drain
521  BMA250E_INT_OUT_CTRL_INT2_LVL = 0x04,
522  BMA250E_INT_OUT_CTRL_INT2_OD = 0x08
523 
524  // 0x10-0x80 reserved
525  } BMA250E_INT_OUT_CTRL_BITS_T;
526 
530  typedef enum {
531  _BMA250E_INT_RST_LATCH_RESERVED_BITS = 0x10 | 0x20 | 0x40,
532 
533  BMA250E_INT_RST_LATCH0 = 0x01,
534  BMA250E_INT_RST_LATCH1 = 0x02,
535  BMA250E_INT_RST_LATCH2 = 0x04,
536  BMA250E_INT_RST_LATCH3 = 0x08,
537  _BMA250E_INT_RST_LATCH_MASK = 15,
538  _BMA250E_INT_RST_LATCH_SHIFT = 0,
539 
540  // 0x10-0x40 reserved
541 
542  BMA250E_INT_RST_LATCH_RESET_INT = 0x80
543  } BMA250E_INT_RST_LATCH_BITS_T;
544 
548  typedef enum {
549  BMA250E_RST_LATCH_NON_LATCHED = 0,
550  BMA250E_RST_LATCH_TEMPORARY_250MS = 1,
551  BMA250E_RST_LATCH_TEMPORARY_500MS = 2,
552  BMA250E_RST_LATCH_TEMPORARY_1S = 3,
553  BMA250E_RST_LATCH_TEMPORARY_2S = 4,
554  BMA250E_RST_LATCH_TEMPORARY_4S = 5,
555  BMA250E_RST_LATCH_TEMPORARY_8S = 6,
556  BMA250E_RST_LATCH_LATCHED = 7,
557 
558  // 8 == non latched
559 
560  BMA250E_RST_LATCH_TEMPORARY_250US = 9,
561  BMA250E_RST_LATCH_TEMPORARY_500US = 10,
562  BMA250E_RST_LATCH_TEMPORARY_1MS = 11,
563  BMA250E_RST_LATCH_TEMPORARY_12_5MS = 12,
564  BMA250E_RST_LATCH_TEMPORARY_25MS = 13,
565  BMA250E_RST_LATCH_TEMPORARY_50MS = 14
566 
567  // 15 == latched
568  } BMA250E_RST_LATCH_T;
569 
573  typedef enum {
574  BMA250E_INT_2_LOW_HY0 = 0x01,
575  BMA250E_INT_2_LOW_HY1 = 0x02,
576  _BMA250E_INT_2_LOW_HY_MASK = 3,
577  _BMA250E_INT_2_LOW_HY_SHIFT = 0,
578 
579  BMA250E_INT_2_LOW_MODE = 0x04,
580 
581  // 0x08-0x20 reserved
582 
583  BMA250E_INT_2_HIGH_HY0 = 0x40,
584  BMA250E_INT_2_HIGH_HY1 = 0x80,
585  _BMA250E_INT_2_HIGH_HY_MASK = 3,
586  _BMA250E_INT_2_HIGH_HY_SHIFT = 6
587  } BMA250E_INT_2_BITS_T;
588 
592  typedef enum {
593  BMA250E_INT_5_SLOPE_DUR0 = 0x01,
594  BMA250E_INT_5_SLOPE_DUR1 = 0x02,
595  _BMA250E_INT_5_SLOPE_DUR_MASK = 3,
596  _BMA250E_INT_5_SLOPE_DUR_SHIFT = 0,
597 
598  BMA250E_INT_5_SLO_NO_MOT_DUR0 = 0x04,
599  BMA250E_INT_5_SLO_NO_MOT_DUR1 = 0x08,
600  BMA250E_INT_5_SLO_NO_MOT_DUR2 = 0x10,
601  BMA250E_INT_5_SLO_NO_MOT_DUR3 = 0x20,
602  BMA250E_INT_5_SLO_NO_MOT_DUR4 = 0x40,
603  BMA250E_INT_5_SLO_NO_MOT_DUR5 = 0x80,
604  _BMA250E_INT_5_SLO_NO_MOT_DUR_MASK = 63,
605  _BMA250E_INT_5_SLO_NO_MOT_DUR_SHIFT = 2
606  } BMA250E_INT_5_BITS_T;
607 
611  typedef enum {
612  BMA250E_INT_8_TAP_DUR0 = 0x01,
613  BMA250E_INT_8_TAP_DUR1 = 0x02,
614  BMA250E_INT_8_TAP_DUR2 = 0x04,
615  _BMA250E_INT_8_TAP_DUR_MASK = 7,
616  _BMA250E_INT_8_TAP_DUR_SHIFT = 0,
617 
618  // 0x08-0x20 reserved
619 
620  BMA250E_INT_8_TAP_SHOCK = 0x40,
621  BMA250E_INT_8_TAP_QUIET = 0x80
622  } BMA250E_INT_8_BITS_T;
623 
627  typedef enum {
628  BMA250E_INT_9_TAP_TH0 = 0x01,
629  BMA250E_INT_9_TAP_TH1 = 0x02,
630  BMA250E_INT_9_TAP_TH2 = 0x04,
631  BMA250E_INT_9_TAP_TH3 = 0x08,
632  BMA250E_INT_9_TAP_TH4 = 0x10,
633  _BMA250E_INT_5_TAP_TH_MASK = 31,
634  _BMA250E_INT_5_TAP_TH_SHIFT = 0,
635 
636  // 0x20 reserved
637 
638  BMA250E_INT_9_TAP_SAMP0 = 0x40,
639  BMA250E_INT_9_TAP_SAMP1 = 0x80,
640  BMA250E_INT_9_TAP_SAMP1_MASK = 3,
641  BMA250E_INT_9_TAP_SAMP1_SHIFT = 6
642  } BMA250E_INT_9_BITS_T;
643 
647  typedef enum {
648  BMA250E_INT_A_ORIENT_MODE0 = 0x01,
649  BMA250E_INT_A_ORIENT_MODE1 = 0x02,
650  _BMA250E_INT_A_ORIENT_MODE_MASK = 3,
651  _BMA250E_INT_A_ORIENT_MODE_SHIFT = 0,
652 
653  BMA250E_INT_A_ORIENT_BLOCKING0 = 0x04,
654  BMA250E_INT_A_ORIENT_BLOCKING1 = 0x08,
655  _BMA250E_INT_A_ORIENT_BLOCKING_MASK = 3,
656  _BMA250E_INT_A_ORIENT_BLOCKING_SHIFT = 2,
657 
658  BMA250E_INT_A_ORIENT_HYST0 = 0x10,
659  BMA250E_INT_A_ORIENT_HYST1 = 0x20,
660  BMA250E_INT_A_ORIENT_HYST2 = 0x40,
661  _BMA250E_INT_A_ORIENT_HYST_MASK = 7,
662  _BMA250E_INT_A_ORIENT_HYST_SHIFT = 4
663 
664  // 0x80 reserved
665  } BMA250E_INT_A_BITS_T;
666 
670  typedef enum {
671  BMA250E_ORIENT_MODE_SYMETRICAL = 0,
672  BMA250E_ORIENT_MODE_HIGH_ASYMETRICAL = 1,
673  BMA250E_ORIENT_MODE_LOW_ASYMETRICAL = 2
674  } BMA250E_ORIENT_MODE_T;
675 
679  typedef enum {
680  BMA250E_ORIENT_BLOCKING_NONE = 0,
681  BMA250E_ORIENT_BLOCKING_THETA_ACC_1_5G = 1,
682  BMA250E_ORIENT_BLOCKING_THETA_ACC_0_2G_1_5G = 2,
683  BMA250E_ORIENT_BLOCKING_THETA_ACC_0_4G_1_5G = 3
684  } BMA250E_ORIENT_BLOCKING_T;
685 
689  typedef enum {
690  BMA250E_INT_B_ORIENT_THETA0 = 0x01,
691  BMA250E_INT_B_ORIENT_THETA1 = 0x02,
692  BMA250E_INT_B_ORIENT_THETA2 = 0x04,
693  BMA250E_INT_B_ORIENT_THETA3 = 0x08,
694  BMA250E_INT_B_ORIENT_THETA4 = 0x10,
695  BMA250E_INT_B_ORIENT_THETA5 = 0x20,
696  _BMA250E_INT_B_ORIENT_THETA_MASK = 63,
697  _BMA250E_INT_B_ORIENT_THETA_SHIFT = 0,
698 
699  BMA250E_INT_B_ORIENT_UD_EN = 0x40
700  // 0x80 reserved
701  } BMA250E_INT_B_BITS_T;
702 
706  typedef enum {
707  BMA250E_INT_B_FLAT_THETA0 = 0x01,
708  BMA250E_INT_B_FLAT_THETA1 = 0x02,
709  BMA250E_INT_B_FLAT_THETA2 = 0x04,
710  BMA250E_INT_B_FLAT_THETA3 = 0x08,
711  BMA250E_INT_B_FLAT_THETA4 = 0x10,
712  BMA250E_INT_B_FLAT_THETA5 = 0x20,
713  _BMA250E_INT_B_FLAT_THETA_MASK = 63,
714  _BMA250E_INT_B_FLAT_THETA_SHIFT = 0,
715 
716  // 0x40-0x80 reserved
717  } BMA250E_INT_C_BITS_T;
718 
722  typedef enum {
723  BMA250E_INT_D_FLAT_HY0 = 0x01,
724  BMA250E_INT_D_FLAT_HY1 = 0x02,
725  BMA250E_INT_D_FLAT_HY2 = 0x04,
726  _BMA250E_INT_B_FLAT_HY_MASK = 7,
727  _BMA250E_INT_B_FLAT_HY_SHIFT = 0,
728 
729  // 0x08 reserved
730 
731  BMA250E_INT_D_FLAT_HOLD_TIME0 = 0x10,
732  BMA250E_INT_D_FLAT_HOLD_TIME1 = 0x20,
733  _BMA250E_INT_B_FLAT_HOLD_TIME_MASK = 3,
734  _BMA250E_INT_B_FLAT_HOLD_TIME_SHIFT = 4
735 
736  // 0x40-0x80 reserved
737  } BMA250E_INT_D_BITS_T;
738 
742  typedef enum {
743  _BMA250E_FIFO_CONFIG_0_RESERVED_BITS = 0x80 | 0x40,
744 
745  BMA250E_FIFO_CONFIG_0_WATER_MARK0 = 0x01,
746  BMA250E_FIFO_CONFIG_0_WATER_MARK1 = 0x02,
747  BMA250E_FIFO_CONFIG_0_WATER_MARK2 = 0x04,
748  BMA250E_FIFO_CONFIG_0_WATER_MARK3 = 0x08,
749  BMA250E_FIFO_CONFIG_0_WATER_MARK4 = 0x10,
750  BMA250E_FIFO_CONFIG_0_WATER_MARK5 = 0x20,
751  _BMA250E_FIFO_CONFIG_0_WATER_MARK_MASK = 63,
752  _BMA250E_FIFO_CONFIG_0_WATER_MARK_SHIFT = 0
753  } BMA250E_FIFO_CONFIG_0_BITS_T;
754 
758  typedef enum {
759  BMA250E_PMU_SELFTTEST_AXIS0 = 0x01,
760  BMA250E_PMU_SELFTTEST_AXIS1 = 0x02,
761  _BMA250E_PMU_SELFTTEST_AXIS_MASK = 3,
762  _BMA250E_PMU_SELFTTEST_AXIS_SHIFT = 0,
763 
764  BMA250E_PMU_SELFTTEST_SIGN = 0x04,
765 
766  // 0x08 reserved
767 
768  BMA250E_PMU_SELFTTEST_AMP = 0x10,
769 
770  // 0x20-0x80 reserved
771  } BMA250E_PMU_SELFTTEST_BITS_T;
772 
776  typedef enum {
777  BMA250E_SELFTTEST_AXIS_NONE = 0,
778  BMA250E_SELFTTEST_AXIS_X = 1,
779  BMA250E_SELFTTEST_AXIS_Y = 2,
780  BMA250E_SELFTTEST_AXIS_Z = 3,
781  } BMA250E_SELFTTEST_AXIS_T;
782 
786  typedef enum {
787  BMA250E_TRIM_NVM_CTRL_NVM_PROG_MODE = 0x01,
788  BMA250E_TRIM_NVM_CTRL_NVM_PROG_TRIG = 0x02,
789  BMA250E_TRIM_NVM_CTRL_NVM_PROG_RDY = 0x04,
790  BMA250E_TRIM_NVM_CTRL_NVM_PROG_LOAD = 0x08,
791 
792  BMA250E_TRIM_NVM_CTRL_NVM_REMAIN0 = 0x10,
793  BMA250E_TRIM_NVM_CTRL_NVM_REMAIN1 = 0x20,
794  BMA250E_TRIM_NVM_CTRL_NVM_REMAIN2 = 0x40,
795  BMA250E_TRIM_NVM_CTRL_NVM_REMAIN3 = 0x80,
796  _BMA250E_TRIM_NVM_CTRL_NVM_REMAIN_MASK = 15,
797  _BMA250E_TRIM_NVM_CTRL_NVM_REMAIN_SHIFT = 4
798  } BMA250E_TRIM_NVM_CTRL_BITS_T;
799 
803  typedef enum {
804  _BMA250E_SPI3_WDT_RESERVED_BITS = 0xf0 | 0x08,
805 
806  BMA250E_SPI3_WDT_SPI3 = 0x01, // 3-wire SPI
807  // - NOT
808  // SUPPORTED
809 
810  BMA250E_SPI3_WDT_I2C_WDT_SEL = 0x02,
811  BMA250E_SPI3_WDT_I2C_WDT_EN = 0x04
812 
813  // 0x08-0x80 reserved
814  } BMA250E_SPI3_WDT_BITS_T;
815 
819  typedef enum {
820  BMA250E_OFC_CTRL_HP_X_EN = 0x01,
821  BMA250E_OFC_CTRL_HP_Y_EN = 0x02,
822  BMA250E_OFC_CTRL_HP_Z_EN = 0x04,
823 
824  // 0x08 reserved
825 
826  BMA250E_OFC_CTRL_CAL_RDY = 0x10,
827 
828  BMA250E_OFC_CTRL_CAL_TRIGGER0 = 0x20,
829  BMA250E_OFC_CTRL_CAL_TRIGGER1 = 0x40,
830  _BMA250E_OFC_CTRL_CAL_TRIGGER_MASK = 3,
831  _BMA250E_OFC_CTRL_CAL_TRIGGER_SHIFT = 5,
832 
833  BMA250E_OFC_CTRL_OFFSET_RESET = 0x80
834 
835  } BMA250E_OFC_CTRL_BITS_T;
836 
840  typedef enum {
841  BMA250E_CAL_TRIGGER_NONE = 0,
842  BMA250E_CAL_TRIGGER_X = 1,
843  BMA250E_CAL_TRIGGER_Y = 2,
844  BMA250E_CAL_TRIGGER_Z = 3
845  } BMA250E_CAL_TRIGGER_T;
846 
850  typedef enum {
851  BMA250E_OFC_SETTING_CUT_OFF = 0x01,
852 
853  BMA250E_OFC_SETTING_OFFSET_TARGET_X0 = 0x02,
854  BMA250E_OFC_SETTING_OFFSET_TARGET_X1 = 0x04,
855  _BMA250E_OFC_SETTING_OFFSET_TARGET_X_MASK = 3,
856  _BMA250E_OFC_SETTING_OFFSET_TARGET_X_SHIFT = 1,
857 
858  BMA250E_OFC_SETTING_OFFSET_TARGET_Y0 = 0x08,
859  BMA250E_OFC_SETTING_OFFSET_TARGET_Y1 = 0x10,
860  _BMA250E_OFC_SETTING_OFFSET_TARGET_Y_MASK = 3,
861  _BMA250E_OFC_SETTING_OFFSET_TARGET_Y_SHIFT = 3,
862 
863  BMA250E_OFC_SETTING_OFFSET_TARGET_Z0 = 0x20,
864  BMA250E_OFC_SETTING_OFFSET_TARGET_Z1 = 0x40,
865  _BMA250E_OFC_SETTING_OFFSET_TARGET_Z_MASK = 3,
866  _BMA250E_OFC_SETTING_OFFSET_TARGET_Z_SHIFT = 5
867 
868  // 0x80 reserved
869  } BMA250E_OFC_SETTING_BITS_T;
870 
874  typedef enum {
875  BMA250E_OFFSET_TARGET_0G = 0,
876  BMA250E_OFFSET_TARGET_PLUS_1G = 1,
877  BMA250E_OFFSET_TARGET_MINUS_1G = 2,
878  // 3 == 0G
879  } BMA250E_OFFSET_TARGET_T;
880 
884  typedef enum {
885  BMA250E_FIFO_CONFIG_1_FIFO_DATA_SEL0 = 0x01,
886  BMA250E_FIFO_CONFIG_1_FIFO_DATA_SEL1 = 0x02,
887  _BMA250E_FIFO_CONFIG_1_FIFO_DATA_SEL = 3,
888  _BMA250E_FIFO_CONFIG_1_FIFO_DATA_SHIFT = 0,
889 
890  // 0x04-0x20 reserved
891 
892  BMA250E_FIFO_CONFIG_1_FIFO_MODE0 = 0x40,
893  BMA250E_FIFO_CONFIG_1_FIFO_MODE1 = 0x80,
894  _BMA250E_FIFO_CONFIG_1_FIFO_MODE_MASK = 3,
895  _BMA250E_FIFO_CONFIG_1_FIFO_MODE_SHIFT = 5
896  } BMA250E_FIFO_CONFIG_1_BITS_T;
897 
901  typedef enum {
902  BMA250E_FIFO_DATA_SEL_XYZ = 0,
903  BMA250E_FIFO_DATA_SEL_X = 1,
904  BMA250E_FIFO_DATA_SEL_Y = 2,
905  BMA250E_FIFO_DATA_SEL_Z = 3
906  } BMA250E_FIFO_DATA_SEL_T;
907 
911  typedef enum {
912  BMA250E_FIFO_MODE_BYPASS = 0,
913  BMA250E_FIFO_MODE_FIFO = 1,
914  BMA250E_FIFO_MODE_STREAM = 2
915 
916  // 3 == reserved (execute self-destruct :)
917  } BMA250E_FIFO_MODE_T;
918 
919  // interrupt selection for installISR() and uninstallISR()
920  typedef enum {
921  BMA250E_INTERRUPT_INT1,
922  BMA250E_INTERRUPT_INT2
923  } BMA250E_INTERRUPT_PINS_T;
924 
925  // Different variants of this chip support different resolutions.
926  // The 0xf9 variant supports 10b, while the 0xfa variant (bmx055)
927  // supports 12 bits.
928  typedef enum {
929  BMA250E_RESOLUTION_10BITS,
930  BMA250E_RESOLUTION_12BITS
931  } BMA250E_RESOLUTION_T;
932 
933 #ifdef __cplusplus
934 }
935 #endif
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