upm  1.3.0
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bmg160_defs.h
1 /*
2  * Author: Jon Trulson <jtrulson@ics.com>
3  * Copyright (c) 2017 Intel Corporation.
4  *
5  * The MIT License
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining
8  * a copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sublicense, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be
16  * included in all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
21  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26 #pragma once
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 #define BMG160_DEFAULT_I2C_BUS 0
33 #define BMG160_DEFAULT_SPI_BUS 0
34 #define BMG160_DEFAULT_ADDR 0x68
35 
36 // special reset byte
37 #define BMG160_RESET_BYTE 0xb6
38 
39 #define BMG160_CHIPID 0x0f
40 
41  // NOTE: Reserved registers must not be written into. Reading
42  // from them may return indeterminate values. Registers
43  // containing reserved bitfields must be written as 0. Reading
44  // reserved bitfields may return indeterminate values.
45 
49  typedef enum {
50  BMG160_REG_CHIP_ID = 0x00,
51 
52  // 0x01 reserved
53 
54  BMG160_REG_RATE_X_LSB = 0x02,
55  BMG160_REG_RATE_X_MSB = 0x03,
56  BMG160_REG_RATE_Y_LSB = 0x04,
57  BMG160_REG_RATE_Y_MSB = 0x05,
58  BMG160_REG_RATE_Z_LSB = 0x06,
59  BMG160_REG_RATE_Z_MSB = 0x07,
60 
61  BMG160_REG_TEMP = 0x08,
62 
63  BMG160_REG_INT_STATUS_0 = 0x09,
64  BMG160_REG_INT_STATUS_1 = 0x0a,
65  BMG160_REG_INT_STATUS_2 = 0x0b,
66  BMG160_REG_INT_STATUS_3 = 0x0c,
67 
68  // 0x0d reserved
69 
70  BMG160_REG_FIFO_STATUS = 0x0e,
71 
72  BMG160_REG_GYR_RANGE = 0x0f,
73  BMG160_REG_GYR_BW = 0x10,
74  BMG160_REG_LPM1 = 0x11,
75  BMG160_REG_LPM2 = 0x12,
76 
77  BMG160_REG_RATE_HBW = 0x13,
78 
79  BMG160_REG_SOFTRESET = 0x14,
80 
81  BMG160_REG_INT_EN_0 = 0x15,
82  BMG160_REG_INT_EN_1 = 0x16,
83 
84  BMG160_REG_INT_MAP_0 = 0x17,
85  BMG160_REG_INT_MAP_1 = 0x18,
86  BMG160_REG_INT_MAP_2 = 0x19,
87 
88  BMG160_REG_INT_1A = 0x1a,
89  BMG160_REG_INT_1B = 0x1b,
90  BMG160_REG_INT_1C = 0x1c,
91 
92  // 0x1d reserved
93 
94  BMG160_REG_INT_1E = 0x1e,
95 
96  // 0x1f-0x20 reserved
97 
98  BMG160_REG_INT_RST_LATCH = 0x21,
99 
100  BMG160_REG_HIGH_TH_X = 0x22,
101  BMG160_REG_HIGH_DUR_X = 0x23,
102  BMG160_REG_HIGH_TH_Y = 0x24,
103  BMG160_REG_HIGH_DUR_Y = 0x25,
104  BMG160_REG_HIGH_TH_Z = 0x26,
105  BMG160_REG_HIGH_DUR_Z = 0x27,
106 
107  // 0x28-0x30 reserved
108 
109  BMG160_REG_SOC = 0x31,
110  BMG160_REG_A_FOC = 0x32,
111 
112  BMG160_REG_TRIM_NVM_CTRL = 0x33,
113 
114  BMG160_REG_SPI3_WDT = 0x34,
115 
116  // 0x35 reserved
117 
118  BMG160_REG_OFC1 = 0x36,
119  BMG160_REG_OFC2 = 0x37,
120  BMG160_REG_OFC3 = 0x38,
121  BMG160_REG_OFC4 = 0x39,
122 
123  BMG160_REG_TRIM_GP0 = 0x3a,
124  BMG160_REG_TRIM_GP1 = 0x3b,
125 
126  BMG160_REG_BIST = 0x3c,
127 
128  BMG160_REG_FIFO_CONFIG_0 = 0x3d,
129  BMG160_REG_FIFO_CONFIG_1 = 0x3e,
130 
131  BMG160_REG_FIFO_DATA = 0x3f
132 
133  } BMG160_REGS_T;
134 
138  typedef enum {
139  _BMG160_INT_STATUS_0_RESERVED_BITS = 0xf0 | 0x08 | 0x01,
140 
141  BMG160_INT_STATUS_0_HIGH_INT = 0x02,
142  BMG160_INT_STATUS_0_ANY_INT = 0x04
143  } BMG160_INT_STATUS_0_BITS_T;
144 
148  typedef enum {
149  _BMG160_INT_STATUS_1_RESERVED_BITS = 0x0f,
150 
151  BMG160_INT_STATUS_1_FIFO_INT = 0x10,
152  BMG160_INT_STATUS_1_FAST_OFFSET_INT = 0x20,
153  BMG160_INT_STATUS_1_AUTO_OFFSET_INT = 0x40,
154  BMG160_INT_STATUS_1_DATA_INT = 0x80
155  } BMG160_INT_STATUS_1_BITS_T;
156 
160  typedef enum {
161  _BMG160_INT_STATUS_2_RESERVED_BITS = 0xf0,
162 
163  BMG160_INT_STATUS_2_ANY_FIRST_X = 0x01,
164  BMG160_INT_STATUS_2_ANY_FIRST_Y = 0x02,
165  BMG160_INT_STATUS_2_ANY_FIRST_Z = 0x04,
166  BMG160_INT_STATUS_2_ANY_SIGN = 0x08
167  } BMG160_INT_STATUS_2_BITS_T;
168 
172  typedef enum {
173  _BMG160_INT_STATUS_3_RESERVED_BITS = 0xf0,
174 
175  BMG160_INT_STATUS_3_HIGH_FIRST_X = 0x01,
176  BMG160_INT_STATUS_3_HIGH_FIRST_Y = 0x02,
177  BMG160_INT_STATUS_3_HIGH_FIRST_Z = 0x04,
178  BMG160_INT_STATUS_3_HIGH_SIGN = 0x08
179  } BMG160_INT_STATUS_3_BITS_T;
180 
184  typedef enum {
185  BMG160_FIFO_STATUS_FRAME_COUNTER0 = 0x01,
186  BMG160_FIFO_STATUS_FRAME_COUNTER1 = 0x02,
187  BMG160_FIFO_STATUS_FRAME_COUNTER2 = 0x04,
188  BMG160_FIFO_STATUS_FRAME_COUNTER3 = 0x08,
189  BMG160_FIFO_STATUS_FRAME_COUNTER4 = 0x10,
190  BMG160_FIFO_STATUS_FRAME_COUNTER5 = 0x20,
191  BMG160_FIFO_STATUS_FRAME_COUNTER6 = 0x40,
192  _BMG160_FIFO_STATUS_FRAME_COUNTER_MASK = 127,
193  _BMG160_FIFO_STATUS_FRAME_COUNTER_SHIFT = 0,
194 
195  BMG160_FIFO_STATUS_FIFO_OVERRUN = 0x80
196  } BMG160_FIFO_STATUS_BITS_T;
197 
201  typedef enum {
202  _BMG160_GYR_RANGE_RESERVED_BITS = 0x20 | 0x10 | 0x08,
203 
204  BMG160_GYR_RANGE0 = 0x01,
205  BMG160_GYR_RANGE1 = 0x02,
206  BMG160_GYR_RANGE2 = 0x04,
207  _BMG160_GYR_RANGE_MASK = 7,
208  _BMG160_GYR_RANGE_SHIFT = 0,
209 
210  BMG160_GYR_RANGE_FIXED0 = 0x40, // bits need
211  // hardcoding
212  // to 0b10
213  BMG160_GYR_RANGE_FIXED1 = 0x80, // for some
214  // odd
215  // reason...
216  _BMG160_GYR_RANGE_FIXED_MASK = 3,
217  _BMG160_GYR_RANGE_FIXED_SHIFT = 6,
218  _BMG160_GYR_RANGE_FIXED_VALUE = 2 // 0b10
219  } BMG160_GYR_RANGE_BITS_T;
220 
224  typedef enum {
225  BMG160_RANGE_2000 = 0, // degrees/sec
226  BMG160_RANGE_1000 = 1,
227  BMG160_RANGE_500 = 2,
228  BMG160_RANGE_250 = 3,
229  BMG160_RANGE_125 = 4
230  } BMG160_RANGE_T;
231 
235  typedef enum {
236  _BMG160_GYR_BW_RESERVED_BITS = 0xf0,
237 
238  BMG160_GYR_BW0 = 0x01,
239  BMG160_GYR_BW1 = 0x02,
240  BMG160_GYR_BW2 = 0x04,
241  BMG160_GYR_BW3 = 0x08,
242  _BMG160_GYR_BW_MASK = 15,
243  _BMG160_GYR_BW_SHIFT = 0
244  } BMG160_GYR_BW_BITS_T;
245 
249  typedef enum {
250  BMG160_BW_2000_UNFILTERED = 0, // ODR/Filter BW
251  BMG160_BW_2000_230 = 1, // ODR 2000Hz,
252  // Filter BW
253  // 230Hz
254  BMG160_BW_1000_116 = 2,
255  BMG160_BW_400_47 = 3,
256  BMG160_BW_200_23 = 4,
257  BMG160_BW_100_12 = 5,
258  BMG160_BW_200_64 = 6,
259  BMG160_BW_100_32 = 7
260  } BMG160_BW_T;
261 
265  typedef enum {
266  // 0x01 reserved
267  _BMG160_LPM1_RESERVED_BITS = 0x40 | 0x10 | 0x01,
268 
269  BMG160_LPM1_SLEEP_DUR0 = 0x02, // sleep dur
270  // in low
271  // power mode
272  BMG160_LPM1_SLEEP_DUR1 = 0x04,
273  BMG160_LPM1_SLEEP_DUR2 = 0x08,
274  _BMG160_LPM1_SLEEP_MASK = 7,
275  _BMG160_LPM1_SLEEP_SHIFT = 1,
276 
277  // These are separate bits, deep_suspend and suspend (and if all
278  // 0, normal). Since only specific combinations are allowed, we
279  // will treat this as a 3 bit bitfield called POWER_MODE.
280  BMG160_LPM1_POWER_MODE0 = 0x20, // deep_suspend
281  BMG160_LPM1_POWER_MODE1 = 0x40, // must always be 0!
282  BMG160_LPM1_POWER_MODE2 = 0x80, // suspend
283  _BMG160_LPM1_POWER_MODE_MASK = 7,
284  _BMG160_LPM1_POWER_MODE_SHIFT = 5
285  } BMG160_LPM1_BITS_T;
286 
290  typedef enum {
291  BMG160_SLEEP_DUR_2 = 0, // 2ms
292  BMG160_SLEEP_DUR_4 = 1,
293  BMG160_SLEEP_DUR_5 = 2,
294  BMG160_SLEEP_DUR_8 = 3,
295  BMG160_SLEEP_DUR_10 = 4,
296  BMG160_SLEEP_DUR_15 = 5,
297  BMG160_SLEEP_DUR_18 = 6,
298  BMG160_SLEEP_DUR_20 = 7
299  } BMG160_SLEEP_DUR_T;
300 
304  typedef enum {
305  BMG160_POWER_MODE_NORMAL = 0,
306  BMG160_POWER_MODE_DEEP_SUSPEND = 1,
307  BMG160_POWER_MODE_SUSPEND = 4
308  } BMG160_POWER_MODE_T;
309 
313  typedef enum {
314  _BMG160_LPM2_RESERVED_BITS = 0x08,
315 
316  BMG160_LPM2_AUTOSLEEP_DUR0 = 0x01,
317  BMG160_LPM2_AUTOSLEEP_DUR1 = 0x02,
318  BMG160_LPM2_AUTOSLEEP_DUR2 = 0x04,
319  _BMG160_LPM2_AUTOSLEEP_DUR_MASK = 7,
320  _BMG160_LPM2_AUTOSLEEP_DUR_SHIFT = 0,
321 
322  BMG160_LPM2_EXT_TRIG_SEL0 = 0x10,
323  BMG160_LPM2_EXT_TRIG_SEL1 = 0x20,
324  _BMG160_LPM2_EXT_TRIG_SEL_MASK = 3,
325  _BMG160_LPM2_EXT_TRIG_SEL_SHIFT = 4,
326 
327  BMG160_LPM2_POWER_SAVE_MODE = 0x40,
328  BMG160_LPM2_FAST_POWERUP = 0x80
329  } BMG160_LPM2_BITS_T;
330 
331 
335  typedef enum {
336  BMG160_AUTOSLEEP_DUR_NONE = 0,
337  BMG160_AUTOSLEEP_DUR_4MS = 1,
338  BMG160_AUTOSLEEP_DUR_5MS = 2,
339  BMG160_AUTOSLEEP_DUR_8MS = 3,
340  BMG160_AUTOSLEEP_DUR_10MS = 4,
341  BMG160_AUTOSLEEP_DUR_15MS = 5,
342  BMG160_AUTOSLEEP_DUR_20MS = 6,
343  BMG160_AUTOSLEEP_DUR_40MS = 7
344  } BMG160_AUTOSLEEP_DUR_T;
345 
349  typedef enum {
350  BMG160_EXT_TRIG_SEL_NONE = 0,
351  BMG160_EXT_TRIG_SEL_INT1 = 1,
352  BMG160_EXT_TRIG_SEL_INT2 = 2,
353  BMG160_EXT_TRIG_SEL_SDO = 3 // if SPI3 mode
354  // (unsupported)
355  } BMG160_EXT_TRIG_SEL_T;
356 
360  typedef enum {
361  _BMG160_RATE_HBW_RESERVED_BITS = 0x0f | 0x10 | 0x20,
362 
363  BMG160_RATE_HBW_SHADOW_DIS = 0x40,
364  BMG160_RATE_HBW_DATA_HIGH_BW = 0x80
365  } BMG160_RATE_HBW_BITS_T;
366 
370  typedef enum {
371  _BMG160_INT_EN_0_RESERVED_BITS = 0x20 | 0x10 | 0x08 | 0x02
372  | 0x01,
373 
374  BMG160_INT_EN_0_AUTO_OFFSET_EN = 0x04,
375 
376  BMG160_INT_EN_0_FIFO_EN = 0x40,
377  BMG160_INT_EN_0_DATA_EN = 0x80
378  } BMG160_INT_EN_0_BITS_T;
379 
383  typedef enum {
384  _BMG160_INT_EN_1_INT1_RESERVED_BITS = 0xf0,
385 
386  BMG160_INT_EN_1_INT1_LVL = 0x01, // level or edge
387  BMG160_INT_EN_1_INT1_OD = 0x02, // push-pull
388  // or open
389  // drain
390  BMG160_INT_EN_1_INT2_LVL = 0x04,
391  BMG160_INT_EN_1_INT2_OD = 0x08
392  } BMG160_INT_EN_1_BITS_T;
393 
397  typedef enum {
398  _BMG160_INT_MAP_0_RESERVED_BITS = 0xf0 | 0x04 | 0x01,
399 
400  BMG160_INT_MAP_0_INT1_ANY = 0x02,
401  BMG160_INT_MAP_0_INT1_HIGH = 0x08
402  } BMG160_INT_MAP_0_BITS_T;
403 
407  typedef enum {
408  BMG160_INT_MAP_1_INT1_DATA = 0x01,
409  BMG160_INT_MAP_1_INT1_FAST_OFFSET = 0x02,
410  BMG160_INT_MAP_1_INT1_FIFO = 0x04,
411  BMG160_INT_MAP_1_INT1_AUTO_OFFSET = 0x08,
412  BMG160_INT_MAP_1_INT2_AUTO_OFFSET = 0x10,
413  BMG160_INT_MAP_1_INT2_FIFO = 0x20,
414  BMG160_INT_MAP_1_INT2_FAST_OFFSET = 0x40,
415  BMG160_INT_MAP_1_INT2_DATA = 0x80
416  } BMG160_INT_MAP_1_BITS_T;
417 
421  typedef enum {
422  _BMG160_INT_1A_RESERVED_BITS = 0xd5,
423 
424  BMG160_INT_1A_ANY_UNFILT_DATA = 0x02,
425  BMG160_INT_1A_HIGH_UNFILT_DATA = 0x08,
426  BMG160_INT_1A_SLOW_OFFSET_UNFILT = 0x20
427  } BMG160_INT_1A_BITS_T;
428 
432  typedef enum {
433  BMG160_INT_1B_ANY_TH0 = 0x01,
434  BMG160_INT_1B_ANY_TH1 = 0x02,
435  BMG160_INT_1B_ANY_TH2 = 0x04,
436  BMG160_INT_1B_ANY_TH3 = 0x08,
437  BMG160_INT_1B_ANY_TH4 = 0x10,
438  BMG160_INT_1B_ANY_TH5 = 0x20,
439  BMG160_INT_1B_ANY_TH6 = 0x40,
440  _BMG160_INT_1B_ANY_TH_MASK = 127,
441  _BMG160_INT_1B_ANY_TH_SHIFT = 0,
442 
443  BMG160_INT_1B_FAST_OFFSET_UNFILT = 0x80
444  } BMG160_INT_1B_BITS_T;
445 
449  typedef enum {
450  _BMG160_INT_1C_RESERVED_BITS = 0x08,
451 
452  BMG160_INT_1C_ANY_EN_X = 0x01,
453  BMG160_INT_1C_ANY_EN_Y = 0x02,
454  BMG160_INT_1C_ANY_EN_Z = 0x04,
455 
456  BMG160_INT_1C_ANY_DUR_SAMPLE0 = 0x10,
457  BMG160_INT_1C_ANY_DUR_SAMPLE1 = 0x20,
458  BMG160_INT_1C_ANY_DUR_SAMPLE_MASK = 3,
459  BMG160_INT_1C_ANY_DUR_SAMPLE_SHIFT = 4,
460 
461  BMG160_INT_1C_AWAKE_DUR0 = 0x40,
462  BMG160_INT_1C_AWAKE_DUR1 = 0x80,
463  BMG160_INT_1C_AWAKE_DUR_MASK = 3,
464  BMG160_INT_1C_AWAKE_DUR_SHIFT = 6
465  } BMG160_INT_1C_BITS_T;
466 
470  typedef enum {
471  BMG160_ANY_DUR_SAMPLE_4 = 0, // samples
472  BMG160_ANY_DUR_SAMPLE_8 = 1,
473  BMG160_ANY_DUR_SAMPLE_12 = 2,
474  BMG160_ANY_DUR_SAMPLE_16 = 3
475  } BMG160_ANY_DUR_SAMPLE_T;
476 
480  typedef enum {
481  BMG160_AWAKE_DUR_SAMPLE_8 = 0, // samples
482  BMG160_AWAKE_DUR_SAMPLE_16 = 1,
483  BMG160_AWAKE_DUR_SAMPLE_32 = 2,
484  BMG160_AWAKE_DUR_SAMPLE_64 = 3
485  } BMG160_AWAKE_DUR_SAMPLE_T;
486 
490  typedef enum {
491  _BMG160_INT_1E_RESERVED_BITS = 0x7f,
492 
493  BMG160_INT_1E_FIFO_WM_EN = 0x80
494  } BMG160_INT_1E_BITS_T;
495 
499  typedef enum {
500  _BMG160_INT_RST_LATCH_RESERVED_BITS = 0x20,
501 
502  BMG160_INT_RST_LATCH0 = 0x01,
503  BMG160_INT_RST_LATCH1 = 0x02,
504  BMG160_INT_RST_LATCH2 = 0x04,
505  BMG160_INT_RST_LATCH3 = 0x08,
506  _BMG160_INT_RST_LATCH_MASK = 15,
507  _BMG160_INT_RST_LATCH_SHIFT = 0,
508 
509  BMG160_INT_RST_LATCH_STATUS_BIT = 0x10,
510 
511  BMG160_INT_RST_LATCH_OFFSET_RESET = 0x40,
512  BMG160_INT_RST_LATCH_RESET_INT = 0x80
513  } BMG160_INT_RST_LATCH_BITS_T;
514 
518  typedef enum {
519  BMG160_RST_LATCH_NON_LATCHED = 0,
520  BMG160_RST_LATCH_TEMPORARY_250MS = 1,
521  BMG160_RST_LATCH_TEMPORARY_500MS = 2,
522  BMG160_RST_LATCH_TEMPORARY_1S = 3,
523  BMG160_RST_LATCH_TEMPORARY_2S = 4,
524  BMG160_RST_LATCH_TEMPORARY_4S = 5,
525  BMG160_RST_LATCH_TEMPORARY_8S = 6,
526  BMG160_RST_LATCH_LATCHED = 7,
527 
528  // 8 == non latched
529 
530  BMG160_RST_LATCH_TEMPORARY_250US = 9,
531  BMG160_RST_LATCH_TEMPORARY_500US = 10,
532  BMG160_RST_LATCH_TEMPORARY_1MS = 11,
533  BMG160_RST_LATCH_TEMPORARY_12_5MS = 12,
534  BMG160_RST_LATCH_TEMPORARY_25MS = 13,
535  BMG160_RST_LATCH_TEMPORARY_50MS = 14
536 
537  // 15 == latched
538  } BMG160_RST_LATCH_T;
539 
543  typedef enum {
544  BMG160_HIGH_TH_EN = 0x01,
545 
546  BMG160_HIGH_TH_TH0 = 0x02,
547  BMG160_HIGH_TH_TH1 = 0x04,
548  BMG160_HIGH_TH_TH2 = 0x08,
549  BMG160_HIGH_TH_TH3 = 0x10,
550  BMG160_HIGH_TH_TH4 = 0x20,
551  _BMG160_HIGH_TH_TH_MASK = 31,
552  _BMG160_HIGH_TH_TH_SHIFT = 1,
553 
554  BMG160_HIGH_TH_HY0 = 0x40,
555  BMG160_HIGH_TH_HY1 = 0x80,
556  _BMG160_HIGH_TH_HY_MASK = 3,
557  _BMG160_HIGH_TH_HY_SHIFT = 6
558  } BMG160_HIGH_TH_BITS_T;
559 
563  typedef enum {
564  BMG160_SOC_SLOW_OFFSET_EN_X = 0x01,
565  BMG160_SOC_SLOW_OFFSET_EN_Y = 0x02,
566  BMG160_SOC_SLOW_OFFSET_EN_Z = 0x04,
567 
568  BMG160_SOC_SLOW_OFFSET_DUR0 = 0x08,
569  BMG160_SOC_SLOW_OFFSET_DUR1 = 0x10,
570  BMG160_SOC_SLOW_OFFSET_DUR2 = 0x20,
571  _BMG160_SOC_SLOW_OFFSET_DUR_MASK = 7,
572  _BMG160_SOC_SLOW_OFFSET_DUR_SHIFT = 3,
573 
574  BMG160_SOC_SLOW_OFFSET_TH0 = 0x40,
575  BMG160_SOC_SLOW_OFFSET_TH1 = 0x80,
576  _BMG160_SOC_SLOW_OFFSET_TH_MASK = 3,
577  _BMG160_SOC_SLOW_OFFSET_TH_SHIFT = 6
578  } BMG160_SOC_BITS_T;
579 
583  typedef enum {
584  BMG160_SLOW_OFFSET_DUR_40MS = 0, // 40ms
585  BMG160_SLOW_OFFSET_DUR_80MS = 1,
586  BMG160_SLOW_OFFSET_DUR_160MS = 2,
587  BMG160_SLOW_OFFSET_DUR_320MS = 3,
588  BMG160_SLOW_OFFSET_DUR_640MS = 4,
589  BMG160_SLOW_OFFSET_DUR_1280MS = 5
590  } BMG160_SLOW_OFFSET_DUR_T;
591 
595  typedef enum {
596  BMG160_SLOW_OFFSET_TH_0_1 = 0, // 0.1 degree/s
597  BMG160_SLOW_OFFSET_TH_0_2 = 1,
598  BMG160_SLOW_OFFSET_TH_0_5 = 2,
599  BMG160_SLOW_OFFSET_TH_1 = 3
600  } BMG160_SLOW_OFFSET_TH_T;
601 
605  typedef enum {
606  BMG160_A_FOC_FAST_OFFSET_EN_X = 0x01,
607  BMG160_A_FOC_FAST_OFFSET_EN_Y = 0x02,
608  BMG160_A_FOC_FAST_OFFSET_EN_Z = 0x04,
609 
610  BMG160_A_FOC_FAST_OFFSET_EN = 0x08,
611 
612  BMG160_A_FOC_FAST_OFFSET_WORDLENGTH0 = 0x10,
613  BMG160_A_FOC_FAST_OFFSET_WORDLENGTH1 = 0x20,
614  _BMG160_A_FOC_FAST_OFFSET_WORDLENGTH_MASK = 3,
615  _BMG160_A_FOC_FAST_OFFSET_WORDLENGTH_SHIFT = 4,
616 
617  BMG160_A_FOC_AUTO_OFFSET_WORDLENGTH0 = 0x40,
618  BMG160_A_FOC_AUTO_OFFSET_WORDLENGTH1 = 0x80,
619  _BMG160_A_FOC_AUTO_OFFSET_WORDLENGTH_MASK = 3,
620  _BMG160_A_FOC_AUTO_OFFSET_WORDLENGTH_SHIFT = 6
621  } BMG160_A_FOC_BITS_T;
622 
626  typedef enum {
627  BMG160_FAST_OFFSET_WORDLENGTH_32 = 0, // samples
628  BMG160_FAST_OFFSET_WORDLENGTH_64 = 1,
629  BMG160_FAST_OFFSET_WORDLENGTH_128 = 2,
630  BMG160_FAST_OFFSET_WORDLENGTH_256 = 3
631  } BMG160_FAST_OFFSET_WORDLENGTH_T;
632 
636  typedef enum {
637  BMG160_AUTO_OFFSET_WORDLENGTH_32 = 0, // samples
638  BMG160_AUTO_OFFSET_WORDLENGTH_64 = 1,
639  BMG160_AUTO_OFFSET_WORDLENGTH_128 = 2,
640  BMG160_AUTO_OFFSET_WORDLENGTH_256 = 3
641  } BMG160_AUTO_OFFSET_WORDLENGTH_T;
642 
646  typedef enum {
647  BMG160_TRIM_NVM_CTRL_NVM_PROG_MODE = 0x01,
648  BMG160_TRIM_NVM_CTRL_NVM_PROG_TRIG = 0x02,
649  BMG160_TRIM_NVM_CTRL_NVM_PROG_RDY = 0x04,
650  BMG160_TRIM_NVM_CTRL_NVM_PROG_LOAD = 0x08,
651 
652  BMG160_TRIM_NVM_CTRL_NVM_REMAIN0 = 0x10,
653  BMG160_TRIM_NVM_CTRL_NVM_REMAIN1 = 0x20,
654  BMG160_TRIM_NVM_CTRL_NVM_REMAIN2 = 0x40,
655  BMG160_TRIM_NVM_CTRL_NVM_REMAIN3 = 0x80,
656  _BMG160_TRIM_NVM_CTRL_NVM_REMAIN_MASK = 15,
657  _BMG160_TRIM_NVM_CTRL_NVM_REMAIN_SHIFT = 4
658  } BMG160_TRIM_NVM_CTRL_BITS_T;
659 
663  typedef enum {
664  _BMG160_SPI3_WDT_RESERVED_BITS = 0xf0 | 0x08,
665 
666  BMG160_SPI3_WDT_SPI3 = 0x01, // 3-wire SPI -
667  // NOT
668  // SUPPORTED
669 
670  BMG160_SPI3_WDT_I2C_WDT_SEL = 0x02,
671  BMG160_SPI3_WDT_I2C_WDT_EN = 0x04
672 
673  // 0x08-0x80 reserved
674  } BMG160_SPI3_WDT_BITS_T;
675 
679  typedef enum {
680  BMG160_OFC1_OFFSET_Z0 = 0x01, // Z lsb (3:1)
681  BMG160_OFC1_OFFSET_Z1 = 0x02,
682  BMG160_OFC1_OFFSET_Z2 = 0x04,
683  _BMG160_OFC1_OFFSET_Z_MASK = 7,
684  _BMG160_OFC1_OFFSET_Z_SHIFT = 0,
685 
686  BMG160_OFC1_OFFSET_Y0 = 0x08, // Y lsb (3:1)
687  BMG160_OFC1_OFFSET_Y1 = 0x10,
688  BMG160_OFC1_OFFSET_Y2 = 0x20,
689  _BMG160_OFC1_OFFSET_Y_MASK = 7,
690  _BMG160_OFC1_OFFSET_Y_SHIFT = 3,
691 
692  BMG160_OFC1_OFFSET_X0 = 0x08, // bits 3:2 of
693  // X lsb. geez
694  BMG160_OFC1_OFFSET_X1 = 0x10,
695  _BMG160_OFC1_OFFSET_X_MASK = 3,
696  _BMG160_OFC1_OFFSET_X_SHIFT = 6
697  } BMG160_OFC1_OFFSET_BITS_T;
698 
702  typedef enum {
703  BMG160_GP0_OFFSET_Z = 0x01, // Z llsb (bit 0)
704  BMG160_GP0_OFFSET_Y = 0x02, // Y llsb (bit 0)
705 
706  BMG160_GP0_OFFSET_X0 = 0x04, // X llsbs (bits 1:0)
707  BMG160_GP0_OFFSET_X1 = 0x08,
708  _BMG160_GP0_OFFSET_X_MASK = 3,
709  _BMG160_GP0_OFFSET_X_SHIFT = 2,
710 
711  BMG160_GP0_GP00 = 0x10,
712  BMG160_GP0_GP01 = 0x20,
713  BMG160_GP0_GP02 = 0x40,
714  BMG160_GP0_GP03 = 0x80,
715  _BMG160_GP0_GP0_MASK = 15,
716  _BMG160_GP0_GP0_SHIFT = 4
717  } BMG160_GP0_BITS_T;
718 
722  typedef enum {
723  _BMG160_BIST_RESERVED_BITS = 0x80 | 0x40 | 0x20 | 0x08,
724 
725  BMG160_BIST_TRIG_BIST = 0x01,
726  BMG160_BIST_BIST_RDY = 0x02,
727  BMG160_BIST_BIST_FAIL = 0x04,
728 
729  BMG160_BIST_RATE_OK = 0x10
730  } BMG160_BIST_BITS_T;
731 
735  typedef enum {
736  BMG160_FIFO_CONFIG_0_WATER_MARK0 = 0x01,
737  BMG160_FIFO_CONFIG_0_WATER_MARK1 = 0x02,
738  BMG160_FIFO_CONFIG_0_WATER_MARK2 = 0x04,
739  BMG160_FIFO_CONFIG_0_WATER_MARK3 = 0x08,
740  BMG160_FIFO_CONFIG_0_WATER_MARK4 = 0x10,
741  BMG160_FIFO_CONFIG_0_WATER_MARK5 = 0x20,
742  BMG160_FIFO_CONFIG_0_WATER_MARK6 = 0x40,
743  _BMG160_FIFO_CONFIG_0_WATER_MARK_MASK = 127,
744  _BMG160_FIFO_CONFIG_0_WATER_MARK_SHIFT = 0,
745 
746  BMG160_FIFO_CONFIG_0_TAG = 0x80
747  } BMG160_FIFO_CONFIG_0_BITS_T;
748 
752  typedef enum {
753  _BMG160_FIFO_CONFIG_1_RESERVED_BITS = 0x20 | 0x10 |0x08 | 0x04,
754 
755  BMG160_FIFO_CONFIG_1_FIFO_DATA_SEL0 = 0x01,
756  BMG160_FIFO_CONFIG_1_FIFO_DATA_SEL1 = 0x02,
757  _BMG160_FIFO_CONFIG_1_FIFO_DATA_SEL = 3,
758  _BMG160_FIFO_CONFIG_1_FIFO_DATA_SHIFT = 0,
759 
760  BMG160_FIFO_CONFIG_1_FIFO_MODE0 = 0x40,
761  BMG160_FIFO_CONFIG_1_FIFO_MODE1 = 0x80,
762  _BMG160_FIFO_CONFIG_1_FIFO_MODE_MASK = 3,
763  _BMG160_FIFO_CONFIG_1_FIFO_MODE_SHIFT = 6
764  } BMG160_FIFO_CONFIG_1_BITS_T;
765 
769  typedef enum {
770  BMG160_FIFO_DATA_SEL_XYZ = 0,
771  BMG160_FIFO_DATA_SEL_X = 1,
772  BMG160_FIFO_DATA_SEL_Y = 2,
773  BMG160_FIFO_DATA_SEL_Z = 3
774  } BMG160_FIFO_DATA_SEL_T;
775 
779  typedef enum {
780  BMG160_FIFO_MODE_BYPASS = 0,
781  BMG160_FIFO_MODE_FIFO = 1,
782  BMG160_FIFO_MODE_STREAM = 2
783  } BMG160_FIFO_MODE_T;
784 
785  // interrupt selection for installISR() and uninstallISR()
786  typedef enum {
787  BMG160_INTERRUPT_INT1,
788  BMG160_INTERRUPT_INT2
789  } BMG160_INTERRUPT_PINS_T;
790 
791 #ifdef __cplusplus
792 }
793 #endif
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