upm  1.3.0
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lsm303agr_defs.h
1 /*
2  * Author: Jon Trulson <jtrulson@ics.com>
3  * Copyright (c) 2017 Intel Corporation.
4  *
5  * The MIT License
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining
8  * a copy of this software and associated documentation files (the
9  * "Software"), to deal in the Software without restriction, including
10  * without limitation the rights to use, copy, modify, merge, publish,
11  * distribute, sublicense, and/or sell copies of the Software, and to
12  * permit persons to whom the Software is furnished to do so, subject to
13  * the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be
16  * included in all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
21  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25  */
26 #pragma once
27 
28 #ifdef __cplusplus
29 extern "C" {
30 #endif
31 
32 
33 #define LSM303AGR_DEFAULT_I2C_BUS 0
34 #define LSM303AGR_DEFAULT_ACC_ADDR 0x19
35 #define LSM303AGR_DEFAULT_MAG_ADDR 0x1e
36 
37 // from the WHO_AM_I_* registers
38 #define LSM303AGR_CHIPID_ACC 0x33
39 #define LSM303AGR_CHIPID_MAG 0x40
40 
41 // This device has 2 I2C addresses - one for the accelerometer (ACC)
42 // and one for the magnetometer (MAG). But, it uses a single register
43 // map. The MAG registers start at 0x40, while the ACC registers
44 // start at 0 and go to 0x3f. We define the cutoff point here so the
45 // register access functions can "automatically" choose the correct
46 // i2c context (MAG or ACC) to use depending on what register is
47 // being accessed.
48 
49 #define LSM303AGR_MAX_ACC_ADDR 0x3f
50 
51 
52  // NOTE: Reserved registers must not be written into or permanent
53  // damage to the device can result. Reading from them may return
54  // indeterminate values. Registers containing reserved bitfields
55  // must be written as 0.
56 
60  typedef enum {
61 
62  // accelerometer registers
63 
64  // 0x00-0x06 reserved
65 
66  LSM303AGR_REG_STATUS_REG_AUX_A = 0x07,
67 
68  // 0x08-0x0b reserved
69 
70  LSM303AGR_REG_OUT_TEMP_L_A = 0x0c,
71  LSM303AGR_REG_OUT_TEMP_H_A = 0x0d,
72 
73  LSM303AGR_REG_INT_COUNTER_REG_A = 0x0e,
74 
75  LSM303AGR_REG_WHO_AM_I_A = 0x0f,
76 
77  // 0x10-0x1e reserved
78 
79  LSM303AGR_REG_TEMP_CFG_REG_A = 0x1f,
80 
81  LSM303AGR_REG_CTRL_REG1_A = 0x20,
82  LSM303AGR_REG_CTRL_REG2_A = 0x21,
83  LSM303AGR_REG_CTRL_REG3_A = 0x22,
84  LSM303AGR_REG_CTRL_REG4_A = 0x23,
85  LSM303AGR_REG_CTRL_REG5_A = 0x24,
86  LSM303AGR_REG_CTRL_REG6_A = 0x25,
87 
88  LSM303AGR_REG_REFERENCE = 0x26,
89 
90  LSM303AGR_REG_STATUS_REG_A = 0x27,
91 
92  LSM303AGR_REG_OUT_X_L_A = 0x28,
93  LSM303AGR_REG_OUT_X_H_A = 0x29,
94  LSM303AGR_REG_OUT_Y_L_A = 0x2a,
95  LSM303AGR_REG_OUT_Y_H_A = 0x2b,
96  LSM303AGR_REG_OUT_Z_L_A = 0x2c,
97  LSM303AGR_REG_OUT_Z_H_A = 0x2d,
98 
99  LSM303AGR_REG_FIFO_CTRL_REG_A = 0x2e,
100  LSM303AGR_REG_FIFO_SRC_REG_A = 0x2f,
101 
102  LSM303AGR_REG_INT1_CFG_A = 0x30,
103  LSM303AGR_REG_INT1_SRC_A = 0x31,
104  LSM303AGR_REG_INT1_THS_A = 0x32,
105  LSM303AGR_REG_INT1_DUR_A = 0x33,
106 
107  LSM303AGR_REG_INT2_CFG_A = 0x34,
108  LSM303AGR_REG_INT2_SRC_A = 0x35,
109  LSM303AGR_REG_INT2_THS_A = 0x36,
110  LSM303AGR_REG_INT2_DUR_A = 0x37,
111 
112  LSM303AGR_REG_CLICK_CFG_A = 0x38,
113  LSM303AGR_REG_CLICK_SRC_A = 0x39,
114  LSM303AGR_REG_CLICK_THS_A = 0x3a,
115 
116  LSM303AGR_REG_TIME_LIMIT = 0x3b,
117  LSM303AGR_REG_TIME_LATENCY_A = 0x3c,
118  LSM303AGR_REG_TIME_WINDOW_A = 0x3d,
119 
120  LSM303AGR_REG_ACT_THS_A = 0x3e,
121  LSM303AGR_REG_ACT_DUR_A = 0x3f,
122 
123  // magnetometer registers
124 
125  // 0x40-0x44 reserved
126 
127  LSM303AGR_REG_OFFSET_X_REG_L_M = 0x45,
128  LSM303AGR_REG_OFFSET_X_REG_H_M = 0x46,
129  LSM303AGR_REG_OFFSET_Y_REG_L_M = 0x47,
130  LSM303AGR_REG_OFFSET_Y_REG_H_M = 0x48,
131  LSM303AGR_REG_OFFSET_Z_REG_L_M = 0x49,
132  LSM303AGR_REG_OFFSET_Z_REG_H_M = 0x4a,
133 
134  // 0x4b-0x4d reserved
135 
136  LSM303AGR_REG_WHO_AM_I_M = 0x4f,
137 
138  // 0x50-0x5f reserved
139 
140  LSM303AGR_REG_CFG_REG_A_M = 0x60,
141  LSM303AGR_REG_CFG_REG_B_M = 0x61,
142  LSM303AGR_REG_CFG_REG_C_M = 0x62,
143 
144  LSM303AGR_REG_INT_CTRL_REG_M = 0x63,
145  LSM303AGR_REG_INT_SRC_REG_M = 0x64,
146  LSM303AGR_REG_INT_THS_L_REG_M = 0x65,
147  LSM303AGR_REG_INT_THS_H_REG_M = 0x66,
148 
149  LSM303AGR_REG_STATUS_REG_M = 0x67,
150 
151  LSM303AGR_REG_OUTX_L_REG_M = 0x68,
152  LSM303AGR_REG_OUTX_H_REG_M = 0x69,
153  LSM303AGR_REG_OUTY_L_REG_M = 0x6a,
154  LSM303AGR_REG_OUTY_H_REG_M = 0x6b,
155  LSM303AGR_REG_OUTZ_L_REG_M = 0x6c,
156  LSM303AGR_REG_OUTZ_H_REG_M = 0x6d
157 
158  // 0x6e-0x6f reserved
159  } LSM303AGR_REGS_T;
160 
161  // Accelerometer registers
162 
166  typedef enum {
167  // 0x01-0x02 reserved
168 
169  LSM303AGR_STATUS_REG_AUX_A_TDA = 0x04, // temp data avail
170 
171  // 0x08-0x20 reserved
172 
173  LSM303AGR_STATUS_REG_AUX_A_TOR = 0x40, // temp data overrun
174 
175  // 0x80 reserved
176  } LSM303AGR_STATUS_REG_AUX_A_BITS_T;
177 
181  typedef enum {
182  // 0x01-0x20 reserved
183 
184  LSM303AGR_TEMP_CFG_REG_A_TEMP_EN0 = 0x40,
185  LSM303AGR_TEMP_CFG_REG_A_TEMP_EN1 = 0x80,
186  _LSM303AGR_TEMP_CFG_REG_A_TEMP_EN_MASK = 3,
187  _LSM303AGR_TEMP_CFG_REG_A_TEMP_EN_SHIFT = 6,
188  } LSM303AGR_TEMP_CFG_REG_A_BITS_T;
189 
193  typedef enum {
194  LSM303AGR_TEMP_EN_OFF = 0,
195  LSM303AGR_TEMP_EN_ON = 3,
196  } LSM303AGR_TEMP_EN_T;
197 
201  typedef enum {
202  LSM303AGR_CTRL_REG1_A_XEN = 0x01, // axis enables
203  LSM303AGR_CTRL_REG1_A_YEN = 0x02,
204  LSM303AGR_CTRL_REG1_A_ZEN = 0x04,
205  LSM303AGR_CTRL_REG1_A_LPEN = 0x08, // low power enable
206 
207  LSM303AGR_CTRL_REG1_A_ODR0 = 0x10, // output data rate
208  LSM303AGR_CTRL_REG1_A_ODR1 = 0x20,
209  LSM303AGR_CTRL_REG1_A_ODR2 = 0x40,
210  LSM303AGR_CTRL_REG1_A_ODR3 = 0x80,
211  _LSM303AGR_CTRL_REG1_A_ODR_MASK = 15,
212  _LSM303AGR_CTRL_REG1_A_ODR_SHIFT = 4,
213  } LSM303AGR_CTRL_REG1_A_BITS_T;
214 
218  typedef enum {
219  LSM303AGR_A_ODR_POWER_DOWN = 0,
220  LSM303AGR_A_ODR_1HZ = 1, // 1Hz, HR/Normal/LP
221  LSM303AGR_A_ODR_10HZ = 2,
222  LSM303AGR_A_ODR_25HZ = 3,
223  LSM303AGR_A_ODR_50HZ = 4,
224  LSM303AGR_A_ODR_100HZ = 5,
225  LSM303AGR_A_ODR_200HZ = 6,
226  LSM303AGR_A_ODR_400HZ = 7,
227  LSM303AGR_A_ODR_1_620KHZ = 8, // 1.620kHz, low power
228  LSM303AGR_A_ODR_1_344KHZ = 9, // 1.344kHZ
229  // HR/Normal,
230  // 5.376kHZ low
231  // power
232  } LSM303AGR_A_ODR_T;
233 
237  typedef enum {
238  LSM303AGR_CTRL_REG2_A_HPIS1 = 0x01,
239  LSM303AGR_CTRL_REG2_A_HPIS2 = 0x02,
240  LSM303AGR_CTRL_REG2_A_HPCLICK = 0x04,
241  LSM303AGR_CTRL_REG2_A_FDS = 0x08,
242  LSM303AGR_CTRL_REG2_A_HPCF1 = 0x10,
243  LSM303AGR_CTRL_REG2_A_HPCF2 = 0x20,
244 
245  LSM303AGR_CTRL_REG2_A_HPM0 = 0x40,
246  LSM303AGR_CTRL_REG2_A_HPM1 = 0x80,
247  _LSM303AGR_CTRL_REG2_A_HPM_MASK = 3,
248  _LSM303AGR_CTRL_REG2_A_HPM_SHIFT = 6,
249  } LSM303AGR_CTRL_REG2_A_BITS_T;
250 
254  typedef enum {
255  LSM303AGR_A_HPM_NORMAL = 0,
256  LSM303AGR_A_HPM_REF = 1,
257  LSM303AGR_A_HPM_NORMAL2 = 2,
258  LSM303AGR_A_HPM_AUTORESET = 3,
259  } LSM303AGR_A_HPM_T;
260 
264  typedef enum {
265  // 0x01 reserved
266 
267  LSM303AGR_CTRL_REG3_A_I1_OVERRUN = 0x02,
268  LSM303AGR_CTRL_REG3_A_I1_WTM = 0x04,
269  LSM303AGR_CTRL_REG3_A_I1_DRDY2 = 0x08,
270  LSM303AGR_CTRL_REG3_A_I1_DRDY1 = 0x10,
271  LSM303AGR_CTRL_REG3_A_I1_AOI2 = 0x20,
272  LSM303AGR_CTRL_REG3_A_I1_AOI1 = 0x40,
273  LSM303AGR_CTRL_REG3_A_I1_CLICK = 0x80,
274  } LSM303AGR_CTRL_REG3_A_BITS_T;
275 
279  typedef enum {
280  LSM303AGR_CTRL_REG4_A_SPI_ENABLE = 0x01, // 3-wire
281  // spi (no
282  // supported!)
283  LSM303AGR_CTRL_REG4_A_ST0 = 0x02,
284  LSM303AGR_CTRL_REG4_A_ST1 = 0x04,
285  _LSM303AGR_CTRL_REG4_A_ST_MASK = 3,
286  _LSM303AGR_CTRL_REG4_A_ST_SHIFT = 1,
287 
288  LSM303AGR_CTRL_REG4_A_HR = 0x08, // high res
289 
290  LSM303AGR_CTRL_REG4_A_FS0 = 0x10, // FS selection
291  LSM303AGR_CTRL_REG4_A_FS1 = 0x20,
292  _LSM303AGR_CTRL_REG4_A_FS_MASK = 3,
293  _LSM303AGR_CTRL_REG4_A_FS_SHIFT = 4,
294 
295  LSM303AGR_CTRL_REG4_A_BLE = 0x40,
296  LSM303AGR_CTRL_REG4_A_BDU = 0x80, // block update
297  } LSM303AGR_CTRL_REG4_A_BITS_T;
298 
302  typedef enum {
303  LSM303AGR_A_ST_NORMAL = 0,
304  LSM303AGR_A_ST_0 = 1,
305  LSM303AGR_A_ST_1 = 2,
306  } LSM303AGR_A_ST_T;
307 
311  typedef enum {
312  LSM303AGR_A_FS_2G = 0, // 2G
313  LSM303AGR_A_FS_4G = 1,
314  LSM303AGR_A_FS_8G = 2,
315  LSM303AGR_A_FS_16G = 3, // 16G
316  } LSM303AGR_A_FS_T;
317 
321  typedef enum {
322  LSM303AGR_CTRL_REG5_A_D4D_INT2 = 0x01,
323  LSM303AGR_CTRL_REG5_A_LIR_INT2 = 0x02,
324  LSM303AGR_CTRL_REG5_A_D4D_INT1 = 0x04,
325  LSM303AGR_CTRL_REG5_A_LIR_INT1 = 0x08,
326 
327  // 0x10-0x20 reserved
328 
329  LSM303AGR_CTRL_REG5_A_FIFO_EN = 0x40,
330  LSM303AGR_CTRL_REG5_A_BOOT = 0x80,
331  } LSM303AGR_CTRL_REG5_A_BITS_T;
332 
336  typedef enum {
337  // 0x01 reserved
338 
339  LSM303AGR_CTRL_REG6_A_H_LACTIVE = 0x02,
340 
341  // 0x04 reserved
342 
343  LSM303AGR_CTRL_REG6_A_P2_ACT = 0x08,
344  LSM303AGR_CTRL_REG6_A_BOOT_I2 = 0x10,
345  LSM303AGR_CTRL_REG6_A_I2_INT2 = 0x20,
346  LSM303AGR_CTRL_REG6_A_I2_INT1 = 0x40,
347  LSM303AGR_CTRL_REG6_A_I2_CLICK_EN = 0x80,
348  } LSM303AGR_CTRL_REG6_A_BITS_T;
349 
353  typedef enum {
354  LSM303AGR_STATUS_REG_A_XDA = 0x01,
355  LSM303AGR_STATUS_REG_A_YDA = 0x02,
356  LSM303AGR_STATUS_REG_A_ZDA = 0x04,
357  LSM303AGR_STATUS_REG_A_ZYXDA = 0x08,
358  LSM303AGR_STATUS_REG_A_XOR = 0x10,
359  LSM303AGR_STATUS_REG_A_YOR = 0x20,
360  LSM303AGR_STATUS_REG_A_ZOR = 0x40,
361  LSM303AGR_STATUS_REG_A_ZYXOR = 0x80,
362  } LSM303AGR_STATUS_REG_A_BITS_T;
363 
367  typedef enum {
368  LSM303AGR_FIFO_CTRL_REG_A_FTH0 = 0x01, // fifo threshold
369  LSM303AGR_FIFO_CTRL_REG_A_FTH1 = 0x02,
370  LSM303AGR_FIFO_CTRL_REG_A_FTH2 = 0x04,
371  LSM303AGR_FIFO_CTRL_REG_A_FTH3 = 0x08,
372  LSM303AGR_FIFO_CTRL_REG_A_FTH4 = 0x10,
373  _LSM303AGR_FIFO_CTRL_REG_A_FTH_MASK = 31,
374  _LSM303AGR_FIFO_CTRL_REG_A_FTH_SHIF = 0,
375 
376  LSM303AGR_FIFO_CTRL_REG_A_TR = 0x20, // trigger select
377 
378  LSM303AGR_FIFO_CTRL_REG_A_FM0 = 0x40, // fifo mode
379  LSM303AGR_FIFO_CTRL_REG_A_FM1 = 0x80,
380  _LSM303AGR_FIFO_CTRL_REG_A_FM_MASK = 3,
381  _LSM303AGR_FIFO_CTRL_REG_A_FM_SHIFT = 6,
382  } LSM303AGR_FIFO_CTRL_REG_A_BITS_T;
383 
387  typedef enum {
388  LSM303AGR_A_FM_BYPASS = 0,
389  LSM303AGR_A_FM_FIFO = 1,
390  LSM303AGR_A_FM_STREAM = 2,
391  LSM303AGR_A_FM_STREAM_TO_FIFO = 3,
392  } LSM303AGR_A_FM_T;
393 
397  typedef enum {
398  LSM303AGR_FIFO_SRC_REG_A_FSS0 = 0x01, // fifo unread samples
399  LSM303AGR_FIFO_SRC_REG_A_FSS1 = 0x02,
400  LSM303AGR_FIFO_SRC_REG_A_FSS2 = 0x04,
401  LSM303AGR_FIFO_SRC_REG_A_FSS3 = 0x08,
402  LSM303AGR_FIFO_SRC_REG_A_FSS4 = 0x10,
403  _LSM303AGR_FIFO_SRC_REG_A_FSS_MASK = 31,
404  _LSM303AGR_FIFO_SRC_REG_A_FSS_SHIFT = 0,
405 
406  LSM303AGR_FIFO_SRC_REG_A_EMPTY = 0x20,
407  LSM303AGR_FIFO_SRC_REG_A_OVRN_FIFO = 0x40,
408  LSM303AGR_FIFO_SRC_REG_A_WTM = 0x80,
409  } LSM303AGR_FIFO_SRC_REG_A_BITS_T;
410 
414  typedef enum {
415  LSM303AGR_INT_CFG_A_XLIE = 0x01,
416  LSM303AGR_INT_CFG_A_XHIE = 0x02,
417  LSM303AGR_INT_CFG_A_YLIE = 0x04,
418  LSM303AGR_INT_CFG_A_YHIE = 0x08,
419  LSM303AGR_INT_CFG_A_ZLIE = 0x10,
420  LSM303AGR_INT_CFG_A_ZHIE = 0x20,
421  LSM303AGR_INT_CFG_A_6D = 0x40,
422  LSM303AGR_INT_CFG_A_AOI = 0x80,
423  } LSM303AGR_INT_CFG_A_BITS_T;
424 
428  typedef enum {
429  LSM303AGR_INT_SRC_A_XL = 0x01,
430  LSM303AGR_INT_SRC_A_XH = 0x02,
431  LSM303AGR_INT_SRC_A_YL = 0x04,
432  LSM303AGR_INT_SRC_A_YH = 0x08,
433  LSM303AGR_INT_SRC_A_ZL = 0x10,
434  LSM303AGR_INT_SRC_A_ZH = 0x20,
435  LSM303AGR_INT_SRC_A_IA = 0x40,
436 
437  // 0x80 reserved
438  } LSM303AGR_INT_SRC_A_BITS_T;
439 
443  typedef enum {
444  LSM303AGR_INT_THS0 = 0x01,
445  LSM303AGR_INT_THS1 = 0x02,
446  LSM303AGR_INT_THS2 = 0x04,
447  LSM303AGR_INT_THS3 = 0x08,
448  LSM303AGR_INT_THS4 = 0x10,
449  LSM303AGR_INT_THS5 = 0x20,
450  LSM303AGR_INT_THS6 = 0x40,
451  _LSM303AGR_INT_THS_MASK = 127,
452  _LSM303AGR_INT_THS_SHIFT = 0,
453 
454  // 0x80 reserved
455  } LSM303AGR_INT_THS_BITS_T;
456 
460  typedef enum {
461  LSM303AGR_INT_DUR0 = 0x01,
462  LSM303AGR_INT_DUR1 = 0x02,
463  LSM303AGR_INT_DUR2 = 0x04,
464  LSM303AGR_INT_DUR3 = 0x08,
465  LSM303AGR_INT_DUR4 = 0x10,
466  LSM303AGR_INT_DUR5 = 0x20,
467  LSM303AGR_INT_DUR6 = 0x40,
468  _LSM303AGR_INT_DUR_MASK = 127,
469  _LSM303AGR_INT_DUR_SHIFT = 0,
470 
471  // 0x80 reserved
472  } LSM303AGR_INT_DUR_BITS_T;
473 
477  typedef enum {
478  LSM303AGR_CLICK_CFG_A_XS = 0x01,
479  LSM303AGR_CLICK_CFG_A_XD = 0x02,
480  LSM303AGR_CLICK_CFG_A_YS = 0x04,
481  LSM303AGR_CLICK_CFG_A_YD = 0x08,
482  LSM303AGR_CLICK_CFG_A_ZS = 0x10,
483  LSM303AGR_CLICK_CFG_A_ZD = 0x20,
484 
485  // 0x40-0x80 reserved
486  } LSM303AGR_CLICK_CFG_A_BITS_T;
487 
491  typedef enum {
492  LSM303AGR_CLICK_SRC_A_X = 0x01,
493  LSM303AGR_CLICK_SRC_A_Y = 0x02,
494  LSM303AGR_CLICK_SRC_A_Z = 0x04,
495  LSM303AGR_CLICK_SRC_A_SIGN = 0x08,
496  LSM303AGR_CLICK_SRC_A_SCLICK = 0x10,
497  LSM303AGR_CLICK_SRC_A_DCLICK = 0x20,
498  LSM303AGR_CLICK_SRC_A_IA = 0x40,
499 
500  // 0x80 reserved
501  } LSM303AGR_CLICK_SRC_A_BITS_T;
502 
506  typedef enum {
507  LSM303AGR_CLICK_A_THS0 = 0x01,
508  LSM303AGR_CLICK_A_THS1 = 0x02,
509  LSM303AGR_CLICK_A_THS2 = 0x04,
510  LSM303AGR_CLICK_A_THS3 = 0x08,
511  LSM303AGR_CLICK_A_THS4 = 0x10,
512  LSM303AGR_CLICK_A_THS5 = 0x20,
513  LSM303AGR_CLICK_A_THS6 = 0x40,
514  _LSM303AGR_CLICK_A_THS_MASK = 127,
515  _LSM303AGR_CLICK_A_THS_SHIFT = 0,
516 
517  // 0x80 reserved
518  } LSM303AGR_CLICK_THS_A_BITS_T;
519 
523  typedef enum {
524  LSM303AGR_TIME_LIMIT_A_TLI0 = 0x01,
525  LSM303AGR_TIME_LIMIT_A_TLI1 = 0x02,
526  LSM303AGR_TIME_LIMIT_A_TLI2 = 0x04,
527  LSM303AGR_TIME_LIMIT_A_TLI3 = 0x08,
528  LSM303AGR_TIME_LIMIT_A_TLI4 = 0x10,
529  LSM303AGR_TIME_LIMIT_A_TLI5 = 0x20,
530  LSM303AGR_TIME_LIMIT_A_TLI6 = 0x40,
531  _LSM303AGR_TIME_LIMIT_A_TLI_MASK = 127,
532  _LSM303AGR_TIME_LIMIT_A_TLI_SHIFT = 0,
533 
534  // 0x80 reserved
535  } LSM303AGR_TIME_LIMIT_A_BITS_T;
536 
537  // Magnetometer registers
538 
542  typedef enum {
543  LSM303AGR_CFG_REG_A_M_MD0 = 0x01, // mode select
544  LSM303AGR_CFG_REG_A_M_MD1 = 0x02,
545  _LSM303AGR_CFG_REG_A_M_MD_MASK = 3,
546  _LSM303AGR_CFG_REG_A_M_MD_SHIFT = 0,
547 
548  LSM303AGR_CFG_REG_A_M_ODR0 = 0x04, // output data rate
549  LSM303AGR_CFG_REG_A_M_ODR1 = 0x08,
550  _LSM303AGR_CFG_REG_A_M_ODR_MASK = 3,
551  _LSM303AGR_CFG_REG_A_M_ODR_SHIFT = 2,
552 
553  LSM303AGR_CFG_REG_A_M_LP = 0x10, // low power/hi res
554  LSM303AGR_CFG_REG_A_M_SOFT_RESET = 0x20,
555  LSM303AGR_CFG_REG_A_M_REBOOT = 0x40,
556  LSM303AGR_CFG_REG_A_M_COMP_TEMP_EN = 0x80, // temp compensation
557  } LSM303AGR_CFG_REG_A_M_BITS_T;
558 
562  typedef enum {
563  LSM303AGR_CFG_A_M_MD_CONTINUOUS = 0,
564  LSM303AGR_CFG_A_M_MD_SINGLE = 1,
565  LSM303AGR_CFG_A_M_MD_IDLE = 2,
566  } LSM303AGR_CFG_A_M_MD_T;
567 
571  typedef enum {
572  LSM303AGR_CFG_A_M_ODR_10HZ = 0,
573  LSM303AGR_CFG_A_M_ODR_20HZ = 1,
574  LSM303AGR_CFG_A_M_ODR_50HZ = 2,
575  LSM303AGR_CFG_A_M_ODR_100HZ = 3,
576  } LSM303AGR_CFG_A_M_ODR_T;
577 
581  typedef enum {
582  LSM303AGR_CFG_REG_B_M_LPF = 0x01,
583  LSM303AGR_CFG_REG_B_M_OFF_CANC = 0x02,
584  LSM303AGR_CFG_REG_B_M_SET_FREQ = 0x04,
585  LSM303AGR_CFG_REG_B_M_INT_ON_DATA_OFF = 0x08,
586  LSM303AGR_CFG_REG_B_M_OFF_CANC_ONE_SHOT = 0x10,
587 
588  // 0x20-0x80 reserved
589  } LSM303AGR_CFG_REG_B_M_BITS_T;
590 
594  typedef enum {
595  LSM303AGR_CFG_REG_C_M_INT_MAG = 0x01,
596  LSM303AGR_CFG_REG_C_M_SELF_TEST = 0x02,
597 
598  // 0x04 reserved and MUST be 0 for correct operation
599 
600  LSM303AGR_CFG_REG_C_M_BLE = 0x08,
601  LSM303AGR_CFG_REG_C_M_BDU = 0x10,
602  LSM303AGR_CFG_REG_C_M_I2C_DIS = 0x20, // don't do it...
603  LSM303AGR_CFG_REG_C_M_INT_MAG_PIN = 0x40,
604 
605  // 0x80 reserved
606  } LSM303AGR_CFG_REG_C_M_BITS_T;
607 
611  typedef enum {
612  LSM303AGR_INT_CTRL_REG_M_IEN = 0x01,
613  LSM303AGR_INT_CTRL_REG_M_IEL = 0x02,
614  LSM303AGR_INT_CTRL_REG_M_IEA = 0x04,
615 
616  // 0x08-0x10 reserved and MUST be 0 for correct operation
617 
618  LSM303AGR_INT_CTRL_REG_M_ZIEN = 0x20,
619  LSM303AGR_INT_CTRL_REG_M_YIEN = 0x40,
620  LSM303AGR_INT_CTRL_REG_M_XIEN = 0x80,
621  } LSM303AGR_INT_CTRL_REG_M_BITS_T;
622 
626  typedef enum {
627  LSM303AGR_INT_SRC_REG_M_MROI = 0x02,
628  LSM303AGR_INT_SRC_REG_M_N_TH_S_Z = 0x04,
629  LSM303AGR_INT_SRC_REG_M_N_TH_S_Y = 0x08,
630  LSM303AGR_INT_SRC_REG_M_N_TH_S_X = 0x10,
631  LSM303AGR_INT_SRC_REG_M_P_TH_S_Z = 0x20,
632  LSM303AGR_INT_SRC_REG_M_P_TH_S_Y = 0x40,
633  LSM303AGR_INT_SRC_REG_M_P_TH_S_X = 0x80,
634  } LSM303AGR_INT_SRC_REG_M_BITS_T;
635 
639  typedef enum {
640  LSM303AGR_STATUS_REG_M_XDA = 0x01,
641  LSM303AGR_STATUS_REG_M_YDA = 0x02,
642  LSM303AGR_STATUS_REG_M_ZDA = 0x04,
643  LSM303AGR_STATUS_REG_M_ZYXDA = 0x08,
644  LSM303AGR_STATUS_REG_M_XOR = 0x10,
645  LSM303AGR_STATUS_REG_M_YOR = 0x20,
646  LSM303AGR_STATUS_REG_M_ZOR = 0x40,
647  LSM303AGR_STATUS_REG_M_ZYXOR = 0x80,
648  } LSM303AGR_STATUS_REG_M_BITS_T;
649 
650  // The following enums are used for driver functionality.
651 
656  typedef enum {
657  LSM303AGR_INTERRUPT_ACC_1 = 0, // ACC intr 1
658  LSM303AGR_INTERRUPT_ACC_2 = 1, // ACC intr 2
659  LSM303AGR_INTERRUPT_MAG = 2, // MAG intr
660  } LSM303AGR_INTERRUPT_PINS_T;
661 
666  typedef enum {
667  LSM303AGR_POWER_LOW_POWER = 0,
668  LSM303AGR_POWER_NORMAL = 1,
669  LSM303AGR_POWER_HIGH_RESOLUTION = 2,
670  } LSM303AGR_POWER_MODE_T;
671 
672 
673 #ifdef __cplusplus
674 }
675 #endif
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