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upm
0.4.1
Sensor/Actuator repository for libmraa (v0.8.0)
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upm
0.4.1
Sensor/Actuator repository for libmraa (v0.8.0)
|
H3LIS331DL I2C Accelerometer (400g) library. More...
Data Structures | |
| class | H3LIS331DL |
| API for the H3LIS331DL-based Grove 3-Axis Digital Accelerometer (400g) More... | |
Enumerations | |
| enum | H3LIS331DL_REG_T { REG_WHOAMI = 0x0f, REG_REG1 = 0x20, REG_REG2 = 0x21, REG_REG3 = 0x22, REG_REG4 = 0x23, REG_REG5 = 0x24, REG_HP_FILTER_RESET = 0x25, REG_REFERENCE = 0x26, REG_STATUS = 0x27, REG_OUT_X_L = 0x28, REG_OUT_X_H = 0x29, REG_OUT_Y_L = 0x2a, REG_OUT_Y_H = 0x2b, REG_OUT_Z_L = 0x2c, REG_OUT_Z_H = 0x2d, REG_INT1_CFG = 0x30, REG_INT1_SRC = 0x31, REG_INT1_THS = 0x32, REG_INT1_DUR = 0x33, REG_INT2_CFG = 0x34, REG_INT2_SRC = 0x35, REG_INT2_THS = 0x36, REG_INT2_DUR = 0x37 } |
| enum | REG1_BITS_T { REG1_XEN = 0x01, REG1_YEN = 0x02, REG1_ZEN = 0x04, REG1_DR0 = 0x08, REG1_DR1 = 0x10, REG1_DR_SHIFT = 3, REG1_PM0 = 0x20, REG1_PM1 = 0x40, REG1_PM2 = 0x80, REG1_PM_SHIFT = 5 } |
| enum | DR_BITS_T { DR_50_37 = 0x0, DR_100_74 = 0x1, DR_400_292 = 0x2, DR_1000_780 = 0x3 } |
| enum | PM_BITS_T { PM_POWERDWN = 0x0, PM_NORMAL = 0x1, PM_LP05 = 0x2, PM_LP1 = 0x3, PM_LP2 = 0x4, PM_LP5 = 0x5, PM_LP10 = 0x6 } |
| enum | REG2_BITS_T { REG2_HPCF0 = 0x01, REG2_HPCF1 = 0x02, REG2_HPCF_SHIFT = 0, REG2_HPEN1 = 0x04, REG2_HPEN2 = 0x08, REG2_FDS = 0x10, REG2_HPM0 = 0x20, REG2_HPM1 = 0x40, REG2_HPM_SHIFT = 5, REG2_BOOT = 0x80 } |
| enum | HPCF_BITS_T { HPCF_8 = 0x0, HPCF_16 = 0x1, HPCF_32 = 0x2, HPCF_64 = 0x3 } |
| enum | HPM_BITS_T { HPM_NORMAL0 = 0x0, HPM_REF = 0x1, HPM_NORMAL1 = 0x2 } |
| enum | REG3_BITS_T { REG3_I1_CFG0 = 0x01, REG3_I1_CFG1 = 0x02, REG3_I1_CFG_SHIFT = 0, REG3_LIR1 = 0x04, REG3_I2_CFG0 = 0x08, REG3_I2_CFG1 = 0x10, REG3_I2_CFG_SHIFT = 3, REG3_LIR2 = 0x20, REG3_PP_OD = 0x40, REG3_IHL = 0x80 } |
| enum | I_CFG_BITS_T { I_SRC = 0x0, I_OR = 0x1, I_DR = 0x2, I_BOOTING = 0x3 } |
| enum | REG4_BITS_T { REG4_SIM = 0x01, REG4_FS0 = 0x10, REG4_FS1 = 0x20, REG4_FS_SHIFT = 4, REG4_BLE = 0x40, REG4_BDU = 0x80 } |
| enum | FS_BITS_T { FS_100 = 0x0, FS_200 = 0x1, FS_400 = 0x3 } |
| enum | REG5_BITS_T { REG5_TURNON0 = 0x01, REG5_TURNON1 = 0x02 } |
| enum | STATUS_BITS_T { STATUS_XDA = 0x01, STATUS_YDA = 0x02, STATUS_ZDA = 0x04, STATUS_ZYXDA = 0x08, STATUS_XOR = 0x10, STATUS_YOR = 0x20, STATUS_ZOR = 0x40, STATUS_ZYXOR = 0x80 } |
| enum | INT_CFG_BITS_T { INT_CFG_XLIE = 0x01, INT_CFG_XHIE = 0x02, INT_CFG_YLIE = 0x04, INT_CFG_YHIE = 0x08, INT_CFG_ZLIE = 0x10, INT_CFG_ZHIE = 0x20, INT_CFG_AOI = 0x80 } |
| enum | INT_SRC_BITS_T { INT_SRC_XL = 0x01, INT_SRC_XH = 0x02, INT_SRC_YL = 0x04, INT_SRC_YH = 0x08, INT_SRC_ZL = 0x10, INT_SRC_ZH = 0x20, INT_SRC_IA = 0x40 } |
| enum H3LIS331DL_REG_T |
H3LIS331DL registers
| enum REG1_BITS_T |
REG1 bits
| enum DR_BITS_T |
REG1 DR (output rate) bits
| enum PM_BITS_T |
REG1 PM (power mode) bits
| enum REG2_BITS_T |
REG2 bits
| enum HPCF_BITS_T |
REG2 HPCF (high-pass cutoff frequency) bits
| enum HPM_BITS_T |
REG2 HPM (high-pass filter mode) bits
| enum REG3_BITS_T |
REG3 bits
| enum I_CFG_BITS_T |
REG3 I1/I2 PAD control bits
| enum REG4_BITS_T |
REG4 bits
| enum FS_BITS_T |
REG4 FS (full scale) bits
| enum REG5_BITS_T |
REG5 TURNON (sleep to wake) bits
| enum STATUS_BITS_T |
STATUS bits
| enum INT_CFG_BITS_T |
INT1/INT2 CFG bits
| enum INT_SRC_BITS_T |
INT1/INT2 SRC bits
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1.8.9.1
