28 #include <mraa/common.hpp> 29 #include <mraa/i2c.hpp> 31 #include <mraa/gpio.hpp> 33 #define LSM9DS0_I2C_BUS 1 34 #define LSM9DS0_DEFAULT_XM_ADDR 0x1d 35 #define LSM9DS0_DEFAULT_GYRO_ADDR 0x6b 97 REG_WHO_AM_I_G = 0x0f,
101 REG_CTRL_REG1_G = 0x20,
102 REG_CTRL_REG2_G = 0x21,
103 REG_CTRL_REG3_G = 0x22,
104 REG_CTRL_REG4_G = 0x23,
105 REG_CTRL_REG5_G = 0x24,
107 REG_REFERENCE_G = 0x25,
111 REG_STATUS_REG_G = 0x27,
113 REG_OUT_X_L_G = 0x28,
114 REG_OUT_X_H_G = 0x29,
115 REG_OUT_Y_L_G = 0x2a,
116 REG_OUT_Y_H_G = 0x2b,
117 REG_OUT_Z_L_G = 0x2c,
118 REG_OUT_Z_H_G = 0x2d,
120 REG_FIFO_CTRL_REG_G = 0x2e,
121 REG_FIFO_SRC_REG_G = 0x2f,
123 REG_INT1_CFG_G = 0x30,
124 REG_INT1_SRC_G = 0x31,
126 REG_INT1_TSH_XH_G = 0x32,
127 REG_INT1_TSH_XL_G = 0x33,
128 REG_INT1_TSH_YH_G = 0x34,
129 REG_INT1_TSH_YL_G = 0x35,
130 REG_INT1_TSH_ZH_G = 0x36,
131 REG_INT1_TSH_ZL_G = 0x37,
135 REG_INT1_DURATION_G = 0x38
142 CTRL_REG1_G_YEN = 0x01,
143 CTRL_REG1_G_XEN = 0x02,
144 CTRL_REG1_G_ZEN = 0x04,
145 CTRL_REG1_G_PD = 0x08,
147 CTRL_REG1_G_BW0 = 0x10,
148 CTRL_REG1_G_BW1 = 0x20,
149 _CTRL_REG1_G_BW_MASK = 3,
150 _CTRL_REG1_G_BW_SHIFT = 4,
152 CTRL_REG1_G_DR0 = 0x40,
153 CTRL_REG1_G_DR1 = 0x80,
154 _CTRL_REG1_G_DR_MASK = 3,
155 _CTRL_REG1_G_DR_SHIFT = 6,
166 CTRL_REG1_G_ODR0 = 0x10,
167 CTRL_REG1_G_ODR1 = 0x20,
168 CTRL_REG1_G_ODR2 = 0x40,
169 CTRL_REG1_G_ODR3 = 0x80,
170 _CTRL_REG1_G_ODR_MASK = 15,
171 _CTRL_REG1_G_ODR_SHIFT = 4
202 CTRL_REG2_G_HPCF0 = 0x01,
203 CTRL_REG2_G_HPCF1 = 0x02,
204 CTRL_REG2_G_HPCF2 = 0x04,
205 CTRL_REG2_G_HPCF3 = 0x08,
206 _CTRL_REG2_G_HPCF_MASK = 15,
207 _CTRL_REG2_G_HPCF_SHIFT = 0,
209 CTRL_REG2_G_HPM0 = 0x10,
210 CTRL_REG2_G_HPM1 = 0x20,
211 _CTRL_REG2_G_HPM_MASK = 3,
212 _CTRL_REG2_G_HPM_SHIFT = 4,
244 G_HPM_NORMAL_RESET_HPF = 0,
247 G_HPM_AUTORESET_ON_INTR = 3
254 CTRL_REG3_G_I2_EMPTY = 0x01,
255 CTRL_REG3_G_I2_ORUN = 0x02,
256 CTRL_REG3_G_I2_WTM = 0x04,
257 CTRL_REG3_G_I2_DRDY = 0x08,
258 CTRL_REG3_G_PP_OD = 0x10,
259 CTRL_REG3_G_H_LACTIVE = 0x20,
260 CTRL_REG3_G_I1_BOOT = 0x40,
261 CTRL_REG3_G_I1_INT1 = 0x80,
268 CTRL_REG4_G_SIM = 0x01,
270 CTRL_REG4_G_ST0 = 0x02,
271 CTRL_REG4_G_ST1 = 0x04,
272 _CTRL_REG4_G_ST_MASK = 3,
273 _CTRL_REG4_G_ST_SHIFT = 1,
277 CTRL_REG4_G_FS0 = 0x10,
278 CTRL_REG4_G_FS1 = 0x20,
279 _CTRL_REG4_G_FS_MASK = 3,
280 _CTRL_REG4_G_FS_SHIFT = 4,
282 CTRL_REG4_G_BLE = 0x40,
283 CTRL_REG4_G_BDU = 0x80
314 CTRL_REG5_G_OUTSEL0 = 0x01,
315 CTRL_REG5_G_OUTSEL1 = 0x02,
316 _CTRL_REG5_G_OUTSEL_MASK = 3,
317 _CTRL_REG5_G_OUTSEL_SHIFT = 0,
319 CTRL_REG5_G_INT1SEL0 = 0x04,
320 CTRL_REG5_G_INT1SEL1 = 0x08,
321 _CTRL_REG5_G_INT1SEL_MASK = 3,
322 _CTRL_REG5_G_INT1SEL_SHIFT = 2,
324 CTRL_REG5_G_HPEN = 0x10,
328 CTRL_REG5_G_FIFO_EN = 0x40,
329 CTRL_REG5_G_BOOT = 0x80
348 STATUS_REG_G_XDA = 0x01,
349 STATUS_REG_G_YDA = 0x02,
350 STATUS_REG_G_ZDA = 0x04,
351 STATUS_REG_G_ZYXDA = 0x08,
353 STATUS_REG_G_XOR = 0x10,
354 STATUS_REG_G_YOR = 0x20,
355 STATUS_REG_G_ZOR = 0x40,
356 STATUS_REG_G_ZYXOR = 0x80
363 FIFO_CTRL_REG_G_WTM0 = 0x01,
364 FIFO_CTRL_REG_G_WTM1 = 0x02,
365 FIFO_CTRL_REG_G_WTM2 = 0x04,
366 FIFO_CTRL_REG_G_WTM3 = 0x08,
367 FIFO_CTRL_REG_G_WTM4 = 0x10,
368 _FIFO_CTRL_REG_G_WTM_MASK = 31,
369 _FIFO_CTRL_REG_G_WTM_SHIFT = 0,
371 FIFO_CTRL_REG_G_FM0 = 0x20,
372 FIFO_CTRL_REG_G_FM1 = 0x40,
373 FIFO_CTRL_REG_G_FM2 = 0x80,
374 _FIFO_CTRL_REG_G_FM_MASK = 7,
375 _FIFO_CTRL_REG_G_FM_SHIFT = 5,
389 G_FM_STREAM2FIFO = 3,
390 G_FM_BYPASS2STREAM = 4
400 FIFO_CTRL_REG_G_FSS0 = 0x01,
401 FIFO_CTRL_REG_G_FSS1 = 0x02,
402 FIFO_CTRL_REG_G_FSS2 = 0x04,
403 FIFO_CTRL_REG_G_FSS3 = 0x08,
404 FIFO_CTRL_REG_G_FSS4 = 0x10,
405 _FIFO_CTRL_REG_G_FSS_MASK = 31,
406 _FIFO_CTRL_REG_G_FSS_SHIFT = 0,
408 FIFO_CTRL_REG_G_EMPTY = 0x20,
409 FIFO_CTRL_REG_G_OVRN = 0x40,
410 FIFO_CTRL_REG_G_WTM = 0x80
418 INT1_CFG_G_XLIE = 0x01,
419 INT1_CFG_G_XHIE = 0x02,
420 INT1_CFG_G_YLIE = 0x04,
421 INT1_CFG_G_YHIE = 0x08,
422 INT1_CFG_G_ZLIE = 0x10,
423 INT1_CFG_G_ZHIE = 0x20,
425 INT1_CFG_G_LIR = 0x40,
426 INT1_CFG_G_ANDOR = 0x80
434 INT1_SRC_G_XL = 0x01,
435 INT1_SRC_G_XH = 0x02,
436 INT1_SRC_G_YL = 0x04,
437 INT1_SRC_G_YH = 0x08,
438 INT1_SRC_G_ZL = 0x10,
439 INT1_SRC_G_ZH = 0x20,
455 REG_OUT_TEMP_L_XM = 0x05,
456 REG_OUT_TEMP_H_XM = 0x06,
458 REG_STATUS_REG_M = 0x07,
460 REG_OUT_X_L_M = 0x08,
461 REG_OUT_X_H_M = 0x09,
462 REG_OUT_Y_L_M = 0x0a,
463 REG_OUT_Y_H_M = 0x0b,
464 REG_OUT_Z_L_M = 0x0c,
465 REG_OUT_Z_H_M = 0x0d,
469 REG_WHO_AM_I_XM = 0x0f,
473 REG_INT_CTRL_REG_M = 0x12,
474 REG_INT_SRC_REG_M = 0x13,
476 REG_INT_THS_L_M = 0x14,
477 REG_INT_THS_H_M = 0x15,
479 REG_OFFSET_X_L_M = 0x16,
480 REG_OFFSET_X_H_M = 0x17,
481 REG_OFFSET_Y_L_M = 0x18,
482 REG_OFFSET_Y_H_M = 0x19,
483 REG_OFFSET_Z_L_M = 0x1a,
484 REG_OFFSET_Z_H_M = 0x1b,
486 REG_REFERENCE_X = 0x1c,
487 REG_REFERENCE_Y = 0x1d,
488 REG_REFERENCE_Z = 0x1e,
490 REG_CTRL_REG0_XM = 0x1f,
491 REG_CTRL_REG1_XM = 0x20,
492 REG_CTRL_REG2_XM = 0x21,
493 REG_CTRL_REG3_XM = 0x22,
494 REG_CTRL_REG4_XM = 0x23,
495 REG_CTRL_REG5_XM = 0x24,
496 REG_CTRL_REG6_XM = 0x25,
497 REG_CTRL_REG7_XM = 0x26,
499 REG_STATUS_REG_A = 0x27,
501 REG_OUT_X_L_A = 0x28,
502 REG_OUT_X_H_A = 0x29,
503 REG_OUT_Y_L_A = 0x2a,
504 REG_OUT_Y_H_A = 0x2b,
505 REG_OUT_Z_L_A = 0x2c,
506 REG_OUT_Z_H_A = 0x2d,
508 REG_FIFO_CTRL_REG = 0x2e,
509 REG_FIFO_SRC_REG = 0x2f,
511 REG_INT_GEN_1_REG = 0x30,
512 REG_INT_GEN_1_SRC = 0x31,
513 REG_INT_GEN_1_THS = 0x32,
514 REG_INT_GEN_1_DURATION = 0x33,
516 REG_INT_GEN_2_REG = 0x34,
517 REG_INT_GEN_2_SRC = 0x35,
518 REG_INT_GEN_2_THS = 0x36,
519 REG_INT_GEN_2_DURATION = 0x37,
521 REG_CLICK_CFG = 0x38,
522 REG_CLICK_SRC = 0x39,
523 REG_CLICK_THS = 0x3a,
525 REG_TIME_LIMIT = 0x3b,
526 REG_TIME_LATENCY = 0x3c,
527 REG_TIME_WINDOW = 0x3d,
537 STATUS_REG_M_XMDA = 0x01,
538 STATUS_REG_M_YMDA = 0x02,
539 STATUS_REG_M_ZMDA = 0x04,
540 STATUS_REG_M_ZYXMDA = 0x08,
542 STATUS_REG_M_XMOR = 0x10,
543 STATUS_REG_M_YMOR = 0x20,
544 STATUS_REG_M_ZMOR = 0x40,
545 STATUS_REG_M_ZYXMOR = 0x80
552 INT_CTRL_REG_M_MIEN = 0x01,
553 INT_CTRL_REG_M_4D = 0x02,
554 INT_CTRL_REG_M_IEL = 0x04,
555 INT_CTRL_REG_M_IEA = 0x08,
556 INT_CTRL_REG_M_PP_OD = 0x10,
557 INT_CTRL_REG_M_ZMIEN = 0x20,
558 INT_CTRL_REG_M_YMIEN = 0x40,
559 INT_CTRL_REG_M_XMIEN = 0x80
566 INT_SRC_REG_M_MINT = 0x01,
567 INT_SRC_REG_M_MROI = 0x02,
568 INT_SRC_REG_M_NTH_Z = 0x04,
569 INT_SRC_REG_M_NTH_Y = 0x08,
570 INT_SRC_REG_M_NTH_X = 0x10,
571 INT_SRC_REG_M_PTH_Z = 0x20,
572 INT_SRC_REG_M_PTH_Y = 0x40,
573 INT_SRC_REG_M_PTH_X = 0x80
581 CTRL_REG0_XM_HPIS2 = 0x01,
582 CTRL_REG0_XM_HPIS1 = 0x02,
584 CTRL_REG0_XM_HP_CLICK = 0x04,
588 CTRL_REG0_XM_WTM_LEN = 0x20,
589 CTRL_REG0_XM_FIFO_EN = 0x40,
590 CTRL_REG0_XM_BOOT = 0x80
597 CTRL_REG1_XM_AXEN = 0x01,
598 CTRL_REG1_XM_AYEN = 0x02,
599 CTRL_REG1_XM_AZEN = 0x03,
601 CTRL_REG1_XM_BDU = 0x04,
603 CTRL_REG1_XM_AODR0 = 0x10,
604 CTRL_REG1_XM_AODR1 = 0x20,
605 CTRL_REG1_XM_AODR2 = 0x40,
606 CTRL_REG1_XM_AODR3 = 0x80,
607 _CTRL_REG1_XM_AODR_MASK = 15,
608 _CTRL_REG1_XM_AODR_SHIFT = 4
633 CTRL_REG2_XM_SIM = 0x01,
635 CTRL_REG2_XM_AST0 = 0x02,
636 CTRL_REG2_XM_AST1 = 0x04,
637 _CTRL_REG2_XM_AST_MASK = 3,
638 _CTRL_REG2_XM_AST_SHIFT = 1,
640 CTRL_REG2_XM_AFS0 = 0x08,
641 CTRL_REG2_XM_AFS1 = 0x10,
642 CTRL_REG2_XM_AFS2 = 0x20,
643 _CTRL_REG2_XM_AFS_MASK = 7,
644 _CTRL_REG2_XM_AFS_SHIFT = 3,
646 CTRL_REG2_XM_ABW0 = 0x40,
647 CTRL_REG2_XM_ABW1 = 0x80,
648 _CTRL_REG2_XM_ABW_MASK = 3,
649 _CTRL_REG2_XM_ABW_SHIFT = 6
689 CTRL_REG3_XM_P1_EMPTY = 0x01,
690 CTRL_REG3_XM_P1_DRDYM = 0x02,
691 CTRL_REG3_XM_P1_DRDYA = 0x04,
692 CTRL_REG3_XM_P1_INTM = 0x08,
693 CTRL_REG3_XM_P1_INT2 = 0x10,
694 CTRL_REG3_XM_P1_INT1 = 0x20,
695 CTRL_REG3_XM_P1_TAP = 0x40,
696 CTRL_REG3_XM_P1_BOOT = 0x80
703 CTRL_REG4_XM_P2_WTM = 0x01,
704 CTRL_REG4_XM_P2_OVERRUN = 0x02,
705 CTRL_REG4_XM_P2_DRDYM = 0x04,
706 CTRL_REG4_XM_P2_DRDYA = 0x08,
707 CTRL_REG4_XM_P2_INTM = 0x10,
708 CTRL_REG4_XM_P2_INT2 = 0x20,
709 CTRL_REG4_XM_P2_INT1 = 0x40,
710 CTRL_REG4_XM_P2_TAP = 0x80
717 CTRL_REG5_XM_LIR1 = 0x01,
718 CTRL_REG5_XM_LIR2 = 0x02,
720 CTRL_REG5_XM_ODR0 = 0x04,
721 CTRL_REG5_XM_ODR1 = 0x08,
722 CTRL_REG5_XM_ODR2 = 0x10,
723 _CTRL_REG5_XM_ODR_MASK = 7,
724 _CTRL_REG5_XM_ODR_SHIFT = 2,
726 CTRL_REG5_XM_RES0 = 0x20,
727 CTRL_REG5_XM_RES1 = 0x40,
728 _CTRL_REG5_XM_RES_MASK = 3,
729 _CTRL_REG5_XM_RES_SHIFT = 5,
731 CTRL_REG5_XM_TEMP_EN = 0x80
765 CTRL_REG6_XM_MFS0 = 0x20,
766 CTRL_REG6_XM_MFS1 = 0x40,
767 _CTRL_REG6_XM_MFS_MASK = 3,
768 _CTRL_REG6_XM_MFS_SHIFT = 5
787 CTRL_REG7_XM_MD0 = 0x01,
788 CTRL_REG7_XM_MD1 = 0x02,
789 _CTRL_REG7_XM_MD_MASK = 3,
790 _CTRL_REG7_XM_MD_SHIFT = 0,
792 CTRL_REG7_XM_MLP = 0x04,
796 CTRL_REG7_XM_AFDS = 0x20,
798 CTRL_REG7_XM_AHPM0 = 0x40,
799 CTRL_REG7_XM_AHPM1 = 0x80,
800 _CTRL_REG7_XM_AHPM_MASK = 3,
801 _CTRL_REG7_XM_AHPM_SHIFT = 6
808 XM_MD_CONTINUOUS = 0,
822 XM_AHPM_NORMAL_REF = 0,
823 XM_AHPM_REFERENCE = 1,
825 XM_AHPM_AUTORESET = 3
832 STATUS_REG_A_XADA = 0x01,
833 STATUS_REG_A_YADA = 0x02,
834 STATUS_REG_A_ZADA = 0x04,
835 STATUS_REG_A_ZYXADA = 0x08,
837 STATUS_REG_A_XAOR = 0x10,
838 STATUS_REG_A_YAOR = 0x20,
839 STATUS_REG_A_ZAOR = 0x40,
840 STATUS_REG_A_ZYXAOR = 0x80
847 FIFO_CTRL_REG_FTH0 = 0x01,
848 FIFO_CTRL_REG_FTH1 = 0x02,
849 FIFO_CTRL_REG_FTH2 = 0x04,
850 FIFO_CTRL_REG_FTH3 = 0x08,
851 FIFO_CTRL_REG_FTH4 = 0x10,
852 _FIFO_CTRL_REG_FTH_MASK = 31,
853 _FIFO_CTRL_REG_FTH_SHIFT = 0,
855 FIFO_CTRL_REG_FM0 = 0x20,
856 FIFO_CTRL_REG_FM1 = 0x40,
857 FIFO_CTRL_REG_FM2 = 0x80,
858 _FIFO_CTRL_REG_FM_MASK = 7,
859 _FIFO_CTRL_REG_FM_SHIFT = 5,
884 FIFO_CTRL_REG_FSS0 = 0x01,
885 FIFO_CTRL_REG_FSS1 = 0x02,
886 FIFO_CTRL_REG_FSS2 = 0x04,
887 FIFO_CTRL_REG_FSS3 = 0x08,
888 FIFO_CTRL_REG_FSS4 = 0x10,
889 _FIFO_CTRL_REG_FSS_MASK = 31,
890 _FIFO_CTRL_REG_FSS_SHIFT = 0,
892 FIFO_CTRL_REG_EMPTY = 0x20,
893 FIFO_CTRL_REG_OVRN = 0x40,
894 FIFO_CTRL_REG_WTM = 0x80
902 INT_GEN_X_REG_XLIE_XDOWNE = 0x01,
903 INT_GEN_X_REG_XHIE_XUPE = 0x02,
904 INT_GEN_X_REG_YLIE_YDOWNE = 0x04,
905 INT_GEN_X_REG_YHIE_YUPE = 0x08,
906 INT_GEN_X_REG_ZLIE_ZDOWNE = 0x10,
907 INT_GEN_X_REG_ZHIE_ZUPE = 0x20,
908 INT_GEN_X_REG_6D = 0x40,
909 INT_GEN_X_REG_AOI = 0x80
917 INT_GEN_X_SRC_XL = 0x01,
918 INT_GEN_X_SRC_XH = 0x02,
919 INT_GEN_X_SRC_YL = 0x04,
920 INT_GEN_X_SRC_YH = 0x08,
921 INT_GEN_X_SRC_ZL = 0x10,
922 INT_GEN_X_SRC_ZH = 0x20,
923 INT_GEN_X_SRC_IA = 0x40
932 INT_GEN_X_THS0 = 0x01,
933 INT_GEN_X_THS1 = 0x02,
934 INT_GEN_X_THS2 = 0x04,
935 INT_GEN_X_THS3 = 0x08,
936 INT_GEN_X_THS4 = 0x10,
937 INT_GEN_X_THS5 = 0x20,
938 INT_GEN_X_THS6 = 0x40,
939 _INT_GEN_X_THS_MASK = 127,
940 _INT_GEN_X_THS_SHIFT = 0
949 INT_GEN_X_DUR0 = 0x01,
950 INT_GEN_X_DUR1 = 0x02,
951 INT_GEN_X_DUR2 = 0x04,
952 INT_GEN_X_DUR3 = 0x08,
953 INT_GEN_X_DUR4 = 0x10,
954 INT_GEN_X_DUR5 = 0x20,
955 INT_GEN_X_DUR6 = 0x40,
956 _INT_GEN_X_DUR_MASK = 127,
957 _INT_GEN_X_DUR_SHIFT = 0
966 CLICK_CONFIG_XS = 0x01,
967 CLICK_CONFIG_XD = 0x02,
968 CLICK_CONFIG_YS = 0x04,
969 CLICK_CONFIG_YD = 0x08,
970 CLICK_CONFIG_ZS = 0x10,
971 CLICK_CONFIG_ZD = 0x20
983 CLICK_SRC_SIGN = 0x08,
984 CLICK_SRC_SCLICK = 0x10,
985 CLICK_SRC_DCLICK = 0x20,
995 CLICK_THS_THS0 = 0x01,
996 CLICK_THS_THS1 = 0x02,
997 CLICK_THS_THS2 = 0x04,
998 CLICK_THS_THS3 = 0x08,
999 CLICK_THS_THS4 = 0x10,
1000 CLICK_THS_THS5 = 0x20,
1001 CLICK_THS_THS6 = 0x40,
1002 _CLICK_THS_THS_MASK = 127,
1003 _CLICK_THS_THS_SHIFT = 0
1012 CLICK_TIME_LIMIT_TLI0 = 0x01,
1013 CLICK_TIME_LIMIT_TLI1 = 0x02,
1014 CLICK_TIME_LIMIT_TLI2 = 0x04,
1015 CLICK_TIME_LIMIT_TLI3 = 0x08,
1016 CLICK_TIME_LIMIT_TLI4 = 0x10,
1017 CLICK_TIME_LIMIT_TLI5 = 0x20,
1018 CLICK_TIME_LIMIT_TLI6 = 0x40,
1019 _CLICK_TIME_LIMIT_TLI_MASK = 127,
1020 _CLICK_TIME_LIMIT_TLI_SHIFT = 0
1029 ACT_THS_ACTH0 = 0x01,
1030 ACT_THS_ACTH1 = 0x02,
1031 ACT_THS_ACTH2 = 0x04,
1032 ACT_THS_ACTH3 = 0x08,
1033 ACT_THS_ACTH4 = 0x10,
1034 ACT_THS_ACTH5 = 0x20,
1035 ACT_THS_ACTH6 = 0x40,
1036 _ACT_THS_ACTH_MASK = 127,
1037 _ACT_THS_ACTH_SHIFT = 0
1067 LSM9DS0(
int bus=LSM9DS0_I2C_BUS,
1069 uint8_t gAddress=LSM9DS0_DEFAULT_GYRO_ADDR,
1070 uint8_t xmAddress=LSM9DS0_DEFAULT_XM_ADDR);
1117 uint8_t
readReg(DEVICE_T dev, uint8_t reg);
1128 void readRegs(DEVICE_T dev, uint8_t reg, uint8_t *buffer,
int len);
1138 bool writeReg(DEVICE_T dev, uint8_t reg, uint8_t val);
1431 void installISR(INTERRUPT_PINS_T intr,
int gpio, mraa::Edge level,
1432 void (*isr)(
void *),
void *arg);
1468 static const uint8_t m_autoIncrementMode = 0x80;
1476 mraa::Gpio*& getPin(INTERRUPT_PINS_T intr);
1479 mraa::Gpio *m_gpioG_INT;
1480 mraa::Gpio *m_gpioG_DRDY;
1481 mraa::Gpio *m_gpioXM_GEN1;
1482 mraa::Gpio *m_gpioXM_GEN2;
XM_MD_T
Definition: lsm9ds0.hpp:807
bool setMagnetometerMode(XM_MD_T mode)
Definition: lsm9ds0.cxx:523
INT_CTRL_REG_M_BITS_T
Definition: lsm9ds0.hpp:551
float getTemperature()
Definition: lsm9ds0.cxx:646
void updateTemperature()
Definition: lsm9ds0.cxx:268
INT1_CFG_G_BITS_T
Definition: lsm9ds0.hpp:417
bool setInterruptGen1(uint8_t enables)
Definition: lsm9ds0.cxx:718
CTRL_REG0_XM_BITS_T
Definition: lsm9ds0.hpp:580
FIFO_SRC_REG_G_BITS_T
Definition: lsm9ds0.hpp:399
uint8_t getAccelerometerStatus()
Definition: lsm9ds0.cxx:678
bool setMagnetometerInterruptControl(uint8_t enables)
Definition: lsm9ds0.cxx:703
uint8_t readReg(DEVICE_T dev, uint8_t reg)
Definition: lsm9ds0.cxx:288
INT_SRC_REG_M_BITS_T
Definition: lsm9ds0.hpp:565
CLICK_THS_BITS_T
Definition: lsm9ds0.hpp:994
CLICK_CONFIG_BITS_T
Definition: lsm9ds0.hpp:965
G_HPM_T
Definition: lsm9ds0.hpp:243
bool setMagnetometerODR(XM_ODR_T odr)
Definition: lsm9ds0.cxx:512
ACT_THS_BITS_T
Definition: lsm9ds0.hpp:1028
REG_G_T
Definition: lsm9ds0.hpp:94
XM_AODR_T
Definition: lsm9ds0.hpp:614
XM_ABW_T
Definition: lsm9ds0.hpp:678
CTRL_REG2_G_BITS_T
Definition: lsm9ds0.hpp:201
CTRL_REG4_XM_BITS_T
Definition: lsm9ds0.hpp:702
FM_T
Definition: lsm9ds0.hpp:869
FIFO_SRC_REG_BITS_T
Definition: lsm9ds0.hpp:883
uint8_t getMagnetometerStatus()
Definition: lsm9ds0.cxx:673
void update()
Definition: lsm9ds0.cxx:206
FIFO_CTRL_REG_G_T
Definition: lsm9ds0.hpp:362
uint8_t getInterruptGen2Src()
Definition: lsm9ds0.cxx:738
CTRL_REG3_G_BITS_T
Definition: lsm9ds0.hpp:253
bool setAccelerometerScale(XM_AFS_T scale)
Definition: lsm9ds0.cxx:454
CLICK_SRC_BITS_T
Definition: lsm9ds0.hpp:979
void updateMagnetometer()
Definition: lsm9ds0.cxx:250
bool setGyroscopeODR(G_ODR_T odr)
Definition: lsm9ds0.cxx:377
INT_GEN_X_THS_BITS_T
Definition: lsm9ds0.hpp:931
uint8_t getMagnetometerInterruptControl()
Definition: lsm9ds0.cxx:698
INT_GEN_X_SRC_BITS_T
Definition: lsm9ds0.hpp:916
bool setGyroscopeInterruptConfig(uint8_t enables)
Definition: lsm9ds0.cxx:688
STATUS_REG_G_BITS_T
Definition: lsm9ds0.hpp:347
XM_MFS_T
Definition: lsm9ds0.hpp:776
bool setGyroscopeScale(G_FS_T scale)
Definition: lsm9ds0.cxx:388
bool setMagnetometerResolution(XM_RES_T res)
Definition: lsm9ds0.cxx:501
CLICK_TIME_LIMIT_BITS_T
Definition: lsm9ds0.hpp:1011
G_HPCF_T
Definition: lsm9ds0.hpp:224
API for the LSM9DS0 3-axis Gyroscope, Accelerometer, and Magnetometer.
Definition: lsm9ds0.hpp:80
std::vector< float > getMagnetometer()
Definition: lsm9ds0.cxx:639
uint8_t getGyroscopeInterruptConfig()
Definition: lsm9ds0.cxx:683
bool setGyroscopeEnableAxes(uint8_t axes)
Definition: lsm9ds0.cxx:361
C++ API wrapper for the bh1749 driver.
Definition: a110x.hpp:29
G_ST_T
Definition: lsm9ds0.hpp:290
uint8_t getInterruptGen1Src()
Definition: lsm9ds0.cxx:723
void updateAccelerometer()
Definition: lsm9ds0.cxx:232
uint8_t getGyroscopeStatus()
Definition: lsm9ds0.cxx:668
CTRL_REG4_G_BITS_T
Definition: lsm9ds0.hpp:267
bool setMagnetometerScale(XM_MFS_T scale)
Definition: lsm9ds0.cxx:546
uint8_t getMagnetometerInterruptSrc()
Definition: lsm9ds0.cxx:708
CTRL_REG5_XM_BITS_T
Definition: lsm9ds0.hpp:716
void updateGyroscope()
Definition: lsm9ds0.cxx:214
uint8_t getInterruptGen1()
Definition: lsm9ds0.cxx:713
G_FM_T
Definition: lsm9ds0.hpp:385
CTRL_REG1_XM_BITS_T
Definition: lsm9ds0.hpp:596
bool setMagnetometerLPM(bool enable)
Definition: lsm9ds0.cxx:534
LSM9DS0(int bus=LSM9DS0_I2C_BUS, bool raw=false, uint8_t gAddress=LSM9DS0_DEFAULT_GYRO_ADDR, uint8_t xmAddress=LSM9DS0_DEFAULT_XM_ADDR)
Definition: lsm9ds0.cxx:37
G_INT1OUTSEL_T
Definition: lsm9ds0.hpp:337
uint8_t getInterruptGen2()
Definition: lsm9ds0.cxx:728
STATUS_REG_M_BITS_T
Definition: lsm9ds0.hpp:536
CTRL_REG2_XM_BITS_T
Definition: lsm9ds0.hpp:632
INT_GEN_X_REG_BITS_T
Definition: lsm9ds0.hpp:901
std::vector< float > getAccelerometer()
Definition: lsm9ds0.cxx:625
void readRegs(DEVICE_T dev, uint8_t reg, uint8_t *buffer, int len)
Definition: lsm9ds0.cxx:305
XM_ODR_T
Definition: lsm9ds0.hpp:737
XM_AHPM_T
Definition: lsm9ds0.hpp:817
bool setGyroscopePowerDown(bool enable)
Definition: lsm9ds0.cxx:349
CTRL_REG1_G_BITS_T
Definition: lsm9ds0.hpp:141
bool writeReg(DEVICE_T dev, uint8_t reg, uint8_t val)
Definition: lsm9ds0.cxx:324
CTRL_REG3_XM_BITS_T
Definition: lsm9ds0.hpp:688
INT_GEN_X_DUR_BITS_T
Definition: lsm9ds0.hpp:948
bool setInterruptGen2(uint8_t enables)
Definition: lsm9ds0.cxx:733
REG_XM_T
Definition: lsm9ds0.hpp:452
void installISR(INTERRUPT_PINS_T intr, int gpio, mraa::Edge level, void(*isr)(void *), void *arg)
Definition: lsm9ds0.cxx:744
XM_AST_T
Definition: lsm9ds0.hpp:655
std::vector< float > getGyroscope()
Definition: lsm9ds0.cxx:632
bool setAccelerometerEnableAxes(uint8_t axes)
Definition: lsm9ds0.cxx:427
bool enableTemperatureSensor(bool enable)
Definition: lsm9ds0.cxx:656
XM_RES_T
Definition: lsm9ds0.hpp:751
G_FS_T
Definition: lsm9ds0.hpp:303
G_ODR_T
Definition: lsm9ds0.hpp:177
INT1_SRC_G_BITS_T
Definition: lsm9ds0.hpp:433
bool setAccelerometerODR(XM_AODR_T odr)
Definition: lsm9ds0.cxx:443
CTRL_REG7_XM_BITS_T
Definition: lsm9ds0.hpp:786
CTRL_REG5_G_BITS_T
Definition: lsm9ds0.hpp:313
XM_AFS_T
Definition: lsm9ds0.hpp:665
FIFO_CTRL_REG_T
Definition: lsm9ds0.hpp:846
CTRL_REG6_XM_BITS_T
Definition: lsm9ds0.hpp:762
bool init()
Definition: lsm9ds0.cxx:86
~LSM9DS0()
Definition: lsm9ds0.cxx:78
uint8_t getGyroscopeInterruptSrc()
Definition: lsm9ds0.cxx:693
STATUS_REG_A_BITS_T
Definition: lsm9ds0.hpp:831
void uninstallISR(INTERRUPT_PINS_T intr)
Definition: lsm9ds0.cxx:758